1. The continuous scaling trends of smaller devices, higher operating frequencies, lower power supply voltages, and more functionalities for integrated circuits and systems have made it extremely challenging to design a reliable power delivery network (PDN): Design, process, and operation uncertainties have to be considered simultaneously during the modeling and the optimization for PDN design. This dissertation proposes efficient and accurate models of those uncertainties and develops statistical optimization frameworks of PDN design considering peak noise and resonance noise. Ph.D.’09: Statistical Modeling and Optimization for Power Integrity of VLSI Circuits and Systems Student: Yiyu Shi (yshi@ee.ucla.edu) Advisor: Lei Heyshi@ee.ucla.edu EDA Lab (http://eda.ee.ucla.edu), Electrical Engineering Department, UCLA  Peak Noise – significant when transistors switch and draw dynamic currents –occurs at high frequencies (~GHz) – can be detected and suppressed at design time by means of  topology optimization  decoupling capacitance insertion (decap budgeting) [ICCAD07] “Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations ”, ICCAD 07, Best Paper Finalist “EMPIRE: An Efficient and Compact Multiple-Parameterized Model Order Reduction Method for Physical Optimization ”, TVLSI 09 “SAMSON: A Generalized Second-Order Arnoldi Method for Reducing Multiple Source Linear Network with Susceptance”, ISPD 06 “Scalable Symbolic Model Order Reduction”, BMAS 08. “Clock Frequency Actuator with Efficient Stochastic Current Prediction for Runtime Resonance Noise Reduction”, ASPDAC 09, Best Paper Finalist. “Fast Analysis of Structured Power Grid by Triangularization Based Structure Preserving Model Order Reduction”, DAC 06, Best Paper Finalist Collaborators: Dr. Jinjun Xiong, Dr. Howard Chen, Dr. Richard C.-J. Shi, Dr. Hao Yu, Mr. Wei Yao, Mr. Chun-chen Liu Introduction ModelingOptimizationTypes of Uncertainties  Scalable Symbolic MOR for Early Design Verification [BMAS08] – PDN with portion under design can be represented by the symbolic circuit – Symbols model the portion under design and can be isolated from the circuit by modeling the connection as I/O port  too many ports! – Separate the circuit into a set of independent sub-circuits, each with only one port – Perform reduction for each sub-circuit individually – The system response can be obtained from the superposition of the response of each sub-circuit – The reduced system is sparse regardless of the sparsity of the original circuit  High-order Arnoldi Method for Design Sign-off [ISPD06] – With a-priori info of the input current sources, a high-Arnoldi simulator is proposed to include the input current sources during MOR – SAMSON: Extend the first-order Krylov subspace to high order for better accuracy Experimental results demonstrate that significant resonance noise suppression can be obtained for microprocessors and mobile chips.  Classifications of PDN Operation Uncertainties – Logic-induced correlation:  the current loads at different ports are correlated and cannot reach the maximum at the same time due to the inherent logic dependency – Temporal correlation:  the current at any port cannot attain maximum at all times  depending upon the functionality being performed, currents over clock cycles are correlated  For simplicity of presentation, – Model the current in each clock cycle as a triangular waveform with constant rising/falling time – Partition a circuit into blocks and no correlation between different blocks – Assume there is only temporal correlation within certain number of clock cycles L  Stochastic peak current representation –Partition the peak current values into sets –The set contains peak current values at port k and in clock cycle j, j+L, … –Define as the stochastic variable with the sample set –The correlation between and reflects the temporal correlation between clock cycle j 1 and j 2 –The correlation between and reflects the logic-induced correlation between port k 1 and k 2.  Incorporate process variation effects – Sample each peak current multiple times in the process space and apply the same flow Peak Noise Suppression via On-chip Decap Budgeting Modeling of Design Uncertainties Through Model Order Reduction References & Collaborators Modeling of Operation and Process Uncertainties  We model the load currents at high order Markov process.  The load current in the future can be predicted adaptively.  This allows to change clock frequency before the noise occurs. Resonance Noise Suppression via Frequency Actuator Types of Noise in PDN  Design Uncertainties – PDN design is an iterative task and needs evaluation at each iteration – Resolving the system each time is infeasible due to the large size – How to do it efficiently  at the early design stage (certain part of the PDN is still unknown) [BMAS08]  at the optimization stage (with frequent updates) [ISPD07]  at the sign-off stage (the PDN design is complete with accurate current loads) [ISPD06]  Operation Uncertainties − Crosstalk difference over input vectors − Power supply noise fluctuation over time − Processor temperature variation over workload − Efficient extraction and parameterized modeling for both temporal and spatial correlation [ICCAD07]  Process Uncertainties – Process variation also need to be simultaneously considered [ICCAD07]  Resonance Noise – significant when the spectrum of the load current has harmonic components near the resonance frequency – occurs at a frequency (50MHz~200MHz) much lower than the clock frequency (~GHz) – occurs during certain instruction loops at runtime and is hard to optimize at design-time – can be most effectively reduced at runtime  Change supply voltage  Change clock frequency [ASPDAC09] resonance frequency (~100MHz) Interleave iterative alternative programming with uncertainties models for variation-aware decap budgeting with operation and process variations in the load currents.  Both mean and sigma of the noise are reduced when process variation is considered  The currents are predicted accurately  Existing retroactive method changes clock frequency only after noise violation is detected  Our proactive method changes clock frequency based on prediction clock cycles j, temporal correlation port k, logic-induced correlation The logic-induced correlation coefficient between port k 1 and k 2 at clock cycle j c is The temporal correlation coefficient between clock cycle j 1 and j 2 at port k can be computed as  Parameterized current model via ICA to decouple the stochastic variable set − Each represented by the linear combination of a set of independent stochastic variables r k  Multi-parameterized MOR for Design Optimization [ISPD07] – PDN with variables to be optimized can be represented by the parameterized circuit –Traditional parameterized MOR cannot handle large number of parameters – EMPIRE: a four-step approach Remove the variables with little impact on output  Find a new projection matrix with given (reduced) column number  The subspace spanned by the columns of the new matrix has minimum distance to that of the original matrix