1. SEQUENTIAL LOGIC Digital Integrated Circuits© Prentice Hall 1995 Introduction

2. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Combinational vs. Sequential Logic

3. Sequential Logic Digital Integrated Circuits© Prentice Hall 1995 Introduction

4. Positive Feedback: Bi-Stability Digital Integrated Circuits© Prentice Hall 1995 Introduction

5. Meta-Stability Gain should be larger than 1 in the transition region Digital Integrated Circuits© Prentice Hall 1995 Introduction

6. SR-Flip Flop Q S R Q S R Q Q 1 0 1 0 1 1 0 0 Q 1 0 1 Q 0 1 1 Q Q Digital Integrated Circuits© Prentice Hall 1995 Introduction

7. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Clocked D-Latch D Ck

8. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Pulser D

9. JK- Flip Flop Digital Integrated Circuits© Prentice Hall 1995 Introduction

10. Other Flip-Flops Digital Integrated Circuits© Prentice Hall 1995 Introduction

11. Race Problem Digital Integrated Circuits© Prentice Hall 1995 Introduction

12. Master-Slave Flip-Flop Digital Integrated Circuits© Prentice Hall 1995 Introduction

13. Propagation Delay Based Edge-Triggered Digital Integrated Circuits© Prentice Hall 1995 Introduction

14. Edge Triggered Flip-Flop Digital Integrated Circuits© Prentice Hall 1995 Introduction

15. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction MS D-FF (alternate design) D Ck Trick

16. Flip-Flop: Timing Definitions Digital Integrated Circuits© Prentice Hall 1995 Introduction

17. Maximum Clock Frequency Digital Integrated Circuits© Prentice Hall 1995 Introduction

18. CMOS Clocked SR- FlipFlop Digital Integrated Circuits© Prentice Hall 1995 Introduction

19. CMOS Clocked SR Flip-Flop 1 1 0 0 onoff off->on --> 0 1 <-- on off on ->on ->off Digital Integrated Circuits© MJ Irwin 1998 The Pennsylvaina State University

20. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Memory Circuits

21. Flip-Flop: Transistor Sizing Digital Integrated Circuits© Prentice Hall 1995 Introduction

22. 6 Transistor CMOS SR-Flip Flop Digital Integrated Circuits© Prentice Hall 1995 Introduction

23. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Static Ram Cells

24. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction 6 Transistor Static Ram Feedback == State

25. Charge-Based Storage Digital Integrated Circuits© Prentice Hall 1995 Introduction

26. Master-Slave Flip-Flop Digital Integrated Circuits© Prentice Hall 1995 Introduction

27. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Pass Gate Feedback D-Latch

28. 2 phase non-overlapping clocks Digital Integrated Circuits© Prentice Hall 1995 Introduction

29. 2-phase dynamic flip-flop Digital Integrated Circuits© Prentice Hall 1995 Introduction

30. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Dynamic Shift Register

31. Flip-flop insensitive to clock overlap Digital Integrated Circuits© Prentice Hall 1995 Introduction

32. C 2 MOS avoids Race Conditions Digital Integrated Circuits© Prentice Hall 1995 Introduction

33. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Memory Circuits

34. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Pseudo NMOS Decoder

35. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Tri-State Write Driver

36. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Memory Array

37. StrongArm SA100 Flip-Flop clock D GND V DD Q Q Digital Integrated Circuits© MJ Irwin 1998 The Pennsylvaina State University

38. Power PC Flip-Flop D Q phi Digital Integrated Circuits© MJ Irwin 1998 The Pennsylvaina State University

39. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Dynamic Structures l Lots of variations l Minimize area over complementary structures. l You often (always) need latches anyway. l (why?)

40. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Issues with dynamic logic structures l Timing safety: –"Never" assume that you know the delay of a gate. –Never assume that true/complement clock or data signals are exactly out of phase. –Beware of charge sharing –Don't short the power supply –Extra simulation, not all simulators do a good job on dynamic circuits. –Is there a minimum clock speed, as well as a maximum? –Is the minimum maximum

41. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Combinational/Sequential Datapath Design

42. Pipelining Digital Integrated Circuits© Prentice Hall 1995 Introduction

43. Pipelined Logic using C 2 MOS Digital Integrated Circuits© Prentice Hall 1995 Introduction

44. Example Digital Integrated Circuits© Prentice Hall 1995 Introduction

45. NORA CMOS Modules Digital Integrated Circuits© Prentice Hall 1995 Introduction

46. Doubled C 2 MOS Latches Digital Integrated Circuits© Prentice Hall 1995 Introduction

47. TSPC - True Single Phase Clock Logic Digital Integrated Circuits© Prentice Hall 1995 Introduction

48. Master-Slave Flip-flops Digital Integrated Circuits© Prentice Hall 1995 Introduction

49. Schmitt Trigger VTC with hysteresis Restores signal slopes Digital Integrated Circuits© Prentice Hall 1995 Introduction

50. Noise Suppression using Schmitt Trigger Digital Integrated Circuits© Prentice Hall 1995 Introduction

51. CMOS Schmitt Trigger Moves switching threshold of first inverter Digital Integrated Circuits© Prentice Hall 1995 Introduction

52. Schmitt Trigger Simulated VTC Digital Integrated Circuits© Prentice Hall 1995 Introduction

53. CMOS Schmitt Trigger (2) Digital Integrated Circuits© Prentice Hall 1995 Introduction

54. Multivibrator Circuits Digital Integrated Circuits© Prentice Hall 1995 Introduction

55. Transition-Triggered Monostable Digital Integrated Circuits© Prentice Hall 1995 Introduction

56. Monostable Trigger (RC-based) Digital Integrated Circuits© Prentice Hall 1995 Introduction

57. Astable Multivibrators (Oscillators) Digital Integrated Circuits© Prentice Hall 1995 Introduction

58. Voltage Controller Oscillator (VCO) Digital Integrated Circuits© Prentice Hall 1995 Introduction

59. Relaxation Oscillator Digital Integrated Circuits© Prentice Hall 1995 Introduction

60. Digital Integrated Circuits© Prentice Hall 1995 Introduction

61. Digital Integrated Circuits© MJ Irwin 1998 The Pennsylvaina State University