1. MEMORY ORGANIZATION Memory Hierarchy Main Memory Auxiliary Memory
Associative Memory
Cache Memory
Virtual Memory
Memory Management Hardware

2. MEMORY HIERARCHY Memory Hierarchy is to obtain the highest possible
access speed while minimizing the total cost of the memory system
Auxiliary memory
Magnetic
tapes
I/O
Main
processor
memory
Magnetic
disks
CPU
Cache
memory
Register
Cache
Main Memory
Magnetic Disk
Magnetic Tape

3. MAIN MEMORY RAM and ROM Chips Typical RAM chip Typical ROM chip
Chip select 1
CS1
Chip select 2
CS2
128 x 8
Read RD
8-bit data bus
RAM
Write WR
7-bit address
AD 7
CS1 CS2 RD WR
Memory function
State of data bus
x x
Inhibit
High-impedence
x x
Inhibit
High-impedence
Inhibit
High-impedence
Write
Input data to RAM x
Read
Output data from RAM
x x
Inhibit
High-impedence
Typical ROM chip
Chip select 1
CS1
Chip select 2
CS2
512 x 8
8-bit data bus
ROM
9-bit address
AD 9

4. MEMORY ADDRESS MAP Address space assignment to each memory chip
Main Memory
MEMORY ADDRESS MAP
Address space assignment to each memory chip
Example: 512 bytes RAM and 512 bytes ROM
RAM 1
RAM 2
RAM 3
RAM 4
ROM F FF F FF FF
Component
Hexa
address
x x x x x x x
x x x x x x x
x x x x x x x
x x x x x x x
1 x x x x x x x x x
Address bus
Memory Connection to CPU
- RAM and ROM chips are connected to a CPU
through the data and address buses
- The low-order lines in the address bus select
the byte within the chips and other lines in the
address bus select a particular chip through
its chip select inputs

5. CONNECTION OF MEMORY TO CPU
Main Memory
CONNECTION OF MEMORY TO CPU
CPU
Address bus
16-11 10 9 8
7-1 RD WR
Data bus
Decoder 3 2 1
CS1
CS2 RD
128 x 8
Data
RAM 1 WR
AD7
CS1
CS2 RD
128 x 8
Data
RAM 2 WR
AD7
CS1
CS2 RD
128 x 8
Data
RAM 3 WR
AD7
CS1
CS2 RD
128 x 8
Data
RAM 4 WR
AD7
CS1
CS2
1- 7
512 x 8
Data 8
ROM
AD9 9