Presentation is loading. Please wait.

Presentation is loading. Please wait.

Michae; D.Moffitt ASP-DAC 2008.  Introduction  Algorithms  Experimental results  Conclusions.

Published byHarry Fleming Modified over 9 years ago

Similar presentations

Presentation on theme: "Michae; D.Moffitt ASP-DAC 2008.  Introduction  Algorithms  Experimental results  Conclusions."— Presentation transcript:

1 Michae; D.Moffitt ASP-DAC 2008

2  Introduction  Algorithms  Experimental results  Conclusions

3 Global bins Cells Global edges Global bins Global edges

4 Initial congestion map construction (using FLUTE) Interdependent Net Decomposition Extreme edge shifting Edge Retraction + Garbage Collection Overflow resolved? No Garbage Collection Yes

5 Initial congestion map construction (using FLUTE) Interdependent Net Decomposition Extreme edge shifting Edge Retraction + Garbage Collection Overflow resolved? No Garbage Collection Yes

6 Initial congestion map construction (using FLUTE) Interdependent Net Decomposition Extreme edge shifting Edge Retraction + Garbage Collection Overflow resolved? No Garbage Collection Yes

7 Initial congestion map construction (using FLUTE) Interdependent Net Decomposition Extreme edge shifting Edge Retraction + Garbage Collection Overflow resolved? No Garbage Collection Yes

8 Initial congestion map construction (using FLUTE) Interdependent Net Decomposition Extreme edge shifting Edge Retraction + Garbage Collection Overflow resolved? No Garbage Collection Yes

9 Initial congestion map construction (using FLUTE) Interdependent Net Decomposition Extreme edge shifting Edge Retraction + Garbage Collection Overflow resolved? No Garbage Collection Yes

10 Initial congestion map construction (using FLUTE) Interdependent Net Decomposition Extreme edge shifting Edge Retraction + Garbage Collection Overflow resolved? No Garbage Collection Yes

11 Benchmark (ISPD ‘98) Grids# nets ibm0164x6411507 ibm0280x6418429 ibm0380x6421621 ibm0496x6426163 ibm06128x6433354 ibm07192x6444394 ibm08192x6447944 ibm09256x6450393 ibm10256x6464227 Benchmark (ISPD ‘07) Grids# nets adaptec1324x324219794 adaptec2424x424260159 adaptec3774x779466295 adaptec4774x779515304 adaptec5465x468867411 newblue1399x399331663 newblue2557x463463213 newblue3973x1256551667

12

13 Benchmark FGRMaizeRouterBoxRouterNTHU algorithm Total OFMax OF Total cost (e5) Total OF Max OF Total cost (e5) Total OF Max OF Total cost (e5) Total OF Max OF Total cost (e5) 2- layer adaptec10055.80062.260058.840057.11 adaptec20053.690057.230055.690054.46 adaptec300133.3400137.7500140.8700137.16 adaptec400126.0500128.4500128.7500128.66 adaptec500155.8222176.6900164.3200160.3 newblue112181047.5113481650.93400251.13352447.78 newblue20077.670079.640079.780079.22 newblue3369701090108.18325881236114.63389761088111.6431800608111 6- layer adaptec160290.920099.6100104.050090.56 adaptec250292.190098.1200102.970092.17 adaptec300203.4400214.0800235.8700205.04 adaptec400186.3100194.3800211.9500188.43 adaptec524802264.5822305.3200298.0800265.03 newblue12668492.89134816101.744002101.83352290.91 newblue200136.0800139.6600155.0700136.01 newblue353648636168.42328401058184.4389761088195.531800204168.4

Download ppt "Michae; D.Moffitt ASP-DAC 2008.  Introduction  Algorithms  Experimental results  Conclusions."

Similar presentations

System Level Interconnect Prediction (SLIP) 20081 Sidewinder: A Scalable ILP-Based Router Jin Hu, Jarrod Roy, and Igor Markov Dept. of Computer Science.

System Level Interconnect Prediction (SLIP) Sidewinder: A Scalable ILP-Based Router Jin Hu, Jarrod Roy, and Igor Markov Dept. of Computer Science.
New Graph Bipartizations for Double-Exposure, Bright Field Alternating Phase-Shift Mask Layout Andrew B. Kahng (UCSD) Shailesh Vaya (UCLA) Alex Zelikovsky.

New Graph Bipartizations for Double-Exposure, Bright Field Alternating Phase-Shift Mask Layout Andrew B. Kahng (UCSD) Shailesh Vaya (UCLA) Alex Zelikovsky.
A Graph-Partitioning-Based Approach for Multi-Layer Constrained Via Minimization Yih-Chih Chou and Youn-Long Lin Department of Computer Science, Tsing.

A Graph-Partitioning-Based Approach for Multi-Layer Constrained Via Minimization Yih-Chih Chou and Youn-Long Lin Department of Computer Science, Tsing.
Cadence Design Systems, Inc. Why Interconnect Prediction Doesn’t Work.

Cadence Design Systems, Inc. Why Interconnect Prediction Doesn’t Work.
Optimization of Placement Solutions for Routability Wen-Hao Liu, Cheng-Kok Koh, and Yih-Lang Li DAC’13.

Optimization of Placement Solutions for Routability Wen-Hao Liu, Cheng-Kok Koh, and Yih-Lang Li DAC’13.
An Efficient Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints Rupesh S. Shelar Intel Corporation Hillsboro, OR 97124 Prashant.

An Efficient Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints Rupesh S. Shelar Intel Corporation Hillsboro, OR Prashant.
Wen-Hao Liu1, Yih-Lang Li, and Cheng-Kok Koh Department of Computer Science, National Chiao-Tung University School of Electrical and Computer Engineering,

Wen-Hao Liu1, Yih-Lang Li, and Cheng-Kok Koh Department of Computer Science, National Chiao-Tung University School of Electrical and Computer Engineering,
Natarajan Viswanathan Min Pan Chris Chu Iowa State University International Symposium on Physical Design April 6, 2005 FastPlace: An Analytical Placer.

Natarajan Viswanathan Min Pan Chris Chu Iowa State University International Symposium on Physical Design April 6, 2005 FastPlace: An Analytical Placer.
Meng-Kai Hsu, Sheng Chou, Tzu-Hen Lin, and Yao-Wen Chang Electronics Engineering, National Taiwan University Routability Driven Analytical Placement for.

Meng-Kai Hsu, Sheng Chou, Tzu-Hen Lin, and Yao-Wen Chang Electronics Engineering, National Taiwan University Routability Driven Analytical Placement for.
A Size Scaling Approach for Mixed-size Placement Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan School of Electrical and Computer Engineering.

A Size Scaling Approach for Mixed-size Placement Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan School of Electrical and Computer Engineering.
Ripple: An Effective Routability-Driven Placer by Iterative Cell Movement Xu He, Tao Huang, Linfu Xiao, Haitong Tian, Guxin Cui and Evangeline F.Y. Young.

Ripple: An Effective Routability-Driven Placer by Iterative Cell Movement Xu He, Tao Huang, Linfu Xiao, Haitong Tian, Guxin Cui and Evangeline F.Y. Young.
SimPL: An Effective Placement Algorithm Myung-Chul Kim, Dong-Jin Lee and Igor L. Markov Dept. of EECS, University of Michigan 1ICCAD 2010, Myung-Chul Kim,

SimPL: An Effective Placement Algorithm Myung-Chul Kim, Dong-Jin Lee and Igor L. Markov Dept. of EECS, University of Michigan 1ICCAD 2010, Myung-Chul Kim,
A Depth-First-Search Controlled Gridless Incremental Routing Algorithm for VLSI Circuits Hasan Arslan and Shantanu Dutt Electrical & Computer Eng. University.

A Depth-First-Search Controlled Gridless Incremental Routing Algorithm for VLSI Circuits Hasan Arslan and Shantanu Dutt Electrical & Computer Eng. University.
Paul Falkenstern and Yuan Xie Yao-Wen Chang Yu Wang Three-Dimensional Integrated Circuits (3D IC) Floorplan and Power/Ground Network Co-synthesis ASPDAC’10.

Paul Falkenstern and Yuan Xie Yao-Wen Chang Yu Wang Three-Dimensional Integrated Circuits (3D IC) Floorplan and Power/Ground Network Co-synthesis ASPDAC’10.
1 Physical Hierarchy Generation with Routing Congestion Control Chin-Chih Chang *, Jason Cong *, Zhigang (David) Pan +, and Xin Yuan * * UCLA Computer.

1 Physical Hierarchy Generation with Routing Congestion Control Chin-Chih Chang *, Jason Cong *, Zhigang (David) Pan +, and Xin Yuan * * UCLA Computer.
Shreepad Panth1, Kambiz Samadi2, Yang Du2, and Sung Kyu Lim1

Shreepad Panth1, Kambiz Samadi2, Yang Du2, and Sung Kyu Lim1
An ILP-based Automatic Bus Planner for Dense PCBs P. C. Wu, Q. Ma and M. D. F. Wong Department of Electrical and Computer Engineering, University of Illinois.

An ILP-based Automatic Bus Planner for Dense PCBs P. C. Wu, Q. Ma and M. D. F. Wong Department of Electrical and Computer Engineering, University of Illinois.
Routability-Driven Blockage-Aware Macro Placement Yi-Fang Chen, Chau-Chin Huang, Chien-Hsiung Chiou, Yao-Wen Chang, Chang-Jen Wang.

Routability-Driven Blockage-Aware Macro Placement Yi-Fang Chen, Chau-Chin Huang, Chien-Hsiung Chiou, Yao-Wen Chang, Chang-Jen Wang.
2015-6-11 Layer Assignment Algorithm for RLC Crosstalk Minimization Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong Tsinghua University.

Layer Assignment Algorithm for RLC Crosstalk Minimization Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong Tsinghua University.
International Conference on Computer-Aided Design San Jose, CA Nov. 2001ER UCLA UCLA 1 Congestion Reduction During Placement Based on Integer Programming.

International Conference on Computer-Aided Design San Jose, CA Nov. 2001ER UCLA UCLA 1 Congestion Reduction During Placement Based on Integer Programming.

Similar presentations

Ads by Google