1. 1 Thermal Via Placement in 3D ICs Brent Goplen, Sachin Sapatnekar Department of Electrical and Computer Engineering University of Minnesota

2. 2 Overview Introduction Introduction Simplified Example Simplified Example Formulation Formulation Results Results Conclusions Conclusions

3. 3 3D IC Using Wafer Bonding SOI wafers with bulk substrate removed Adapted from [Das et al., ISVLSI, 2003] Generalized view Bulk wafer Metal level of wafer 1 Layer 1 Layer 2 Layer 3 Layer 4 Layer 5 Bulk Substrate Detailed view Inter-layer bonds Device level 1 500  m 10  m 1m1m

4. 4 Improvements and Obstacles of 3D ICs Benefits Reduced wirelength Reduced wirelength Lower power per transistor Lower power per transistor Decreased delay Decreased delay Higher packing densities Higher packing densities Smaller chip areas Smaller chip areasObstacles Processing technology Processing technology Thermal issues Thermal issues Higher power densities Higher power densities Increased thickness Increased thickness Insulating materials Insulating materials 3D design tools 3D design tools [Joyner, Zarkesh-Ha and Meindl, ASIC/SOC ’01] from Intel

5. 5 Methods of Mitigating Thermal Problems Rearrange heat sources Rearrange heat sources Manually fix hot spots Manually fix hot spots Thermal placement Thermal placement Improved heat sinking Improved heat sinking Improved packaging Improved packaging More efficient heat removal More efficient heat removal Improved thermal conduits Improved thermal conduits Internal heat sinking Internal heat sinking Thermal via placement Thermal via placement Minimize power usage Minimize power usage Low-power design Low-power design Minimize wirelength Minimize wirelength

6. 6 Thermal Via Regions Substrate Thermal Via Thermal vias Thermal vias Electrically isolated vias Electrically isolated vias Used for heat conduction Used for heat conduction Thermal via regions Thermal via regions Only region where thermal vias are allowed Only region where thermal vias are allowed Predictable obstacle for routing Predictable obstacle for routing Variable density of thermal vias Variable density of thermal vias

7. 7 Thermal Vias in 3D ICs Thermal Via Region Inter-Row Region Row Region Standard cells (heat sources) Bulk substrate elements Layer elements Inter-layer elements

8. 8 Benefits and Challenges Benefits Benefits Reduced temperatures Reduced temperatures Uses existing via fabrication Uses existing via fabrication Benefits 3D ICs more Benefits 3D ICs more Challenges Challenges Creates obstacles to routing Creates obstacles to routing Where to put them? Where to put them? CAD tools needed CAD tools needed

9. 9 Overview Introduction Introduction Simplified Example Simplified Example Formulation Formulation Results Results Conclusions Conclusions

10. 10 Simplified Example Layers and inter-layers Bulk Substrate { Thermal Via Regions Heat Sources (standard cells)

11. 11 Simplified Example

12. 12 Simplified Example 456 78 9 10 10W 123 10 o C/W

13. 13 Simplified Example 10W 59 o C81 o C59 o C 32 o C36 o C 32 o C 0oC0oC 65 o C70 o C65 o C 10 o C/W

14. 14 Simplified Example 59 o C81 o C59 o C 32 o C36 o C 32 o C 0oC0oC 10W 10 o C/W 65 o C70 o C65 o C 10 o C/W 6oC6oC6oC6oC 27 o C High Temps High temp drop

15. 15 Simplified Example 59 o C81 o C59 o C 32 o C36 o C 32 o C 0oC0oC 65 o C70 o C65 o C 10 o C/W 11 60 6760

16. 16 Simplified Example 59 o C81 o C59 o C 32 o C36 o C 32 o C 0oC0oC 65 o C70 o C65 o C 10 o C/W 1 1 37 34 64 33 445144 37 Use thermal gradient not temperature!

17. 17 High Temperatures Place Thermal Vias

18. 18 High Thermal Gradients Place Thermal Vias

19. 19 Thermal Via Region High Thermal Via Density High Effective Thermal Conductivities Impractical to place thermal vias individually Impractical to place thermal vias individually Use arrangement of thermal vias instead Use arrangement of thermal vias instead Gives thermal via density value Gives thermal via density value Changes the effective thermal conductivity Changes the effective thermal conductivity

20. 20 High Thermal Conductivity High Thermal Via Density High Thermal Gradients

21. 21 Thermal Gradients Thermal Conductivities Old Temperatures New Temperatures

22. 22 Thermal Gradients Thermal Conductivities Initial Temperatures New Temperatures Thermal Via Densities

23. 23 Mathematical Formulation Heat transfer within an element (region) K ∆T=P Assume P doesn’t change between iterations K new ∆T new = K old ∆T old K new = K old (∆T old / ∆T new ) Using the thermal gradient, g = ∆T /d, K new = K old (g old / g new ) Let g new slowly approach an ideal value, g ideal g new = g ideal (g old / g ideal ) α, 0 ≤ α ≤ 1 K new = K old (g old / g ideal ) 1- α Update g ideal using maximum temperature g ideal = g ideal (T max ideal / T max ) ∆T∆T∆T∆TPK

24. 24 Thermal Via Placement Algorithm GIVEN IDEAL MAXIMUM TEMPERATURE: T max ideal Main loop SET K’s TO MINIMUM AND CALCULATE THERMAL PROFILE UPDATE K z = K z (g / g ideal ) 1- α UPDATE m and K lateral UPDATE g ideal = g ideal T max ideal /T max YES NO DONE CONVERGED? FOR EACH THERMAL VIA REGION CALCULATE THERMAL PROFILE

25. 25 Thermal Conductivities of Thermal Via Regions LayerInterlayer Thermal Conductivity Percent Thermal Via Thermal Conductivity Percent Thermal Via LateralVerticalLateralVertical Minimum2.151.1101.10 0 Midrange3.21100.33251.3150.7112.5 Maximum5.75199.55501.65100.3325

26. 26 Range of Temperature Values Benchmark Circuit Thermal Via Density of Thermal Vias Regions Minimum (0%)Midrange (23.9%)Maximum (47.9%) namecellsT ave T max T ave T max T ave T max struct188815.458.910.935.010.431.3 biomed641714.646.010.524.110.020.2 ibm011228214.245.110.126.29.622.7 ibm042663313.554.010.026.59.621.4 ibm095174613.853.010.226.89.821.4 ibm138150814.647.310.323.69.719.3 ibm1515824415.152.810.526.59.920.6 Midrange thermal via densities produce Midrange thermal via densities produce 47.1% lower maximum temperatures 47.1% lower maximum temperatures 28.3% lower average temperatures 28.3% lower average temperatures

27. 27 Range of Temperature Values Benchmark Circuit Thermal Via Density of Thermal Vias Regions Minimum (0%)Midrange (23.9%)Maximum (47.9%) namecellsT ave T max T ave T max T ave T max struct188815.458.910.935.010.431.3 biomed641714.646.010.524.110.020.2 ibm011228214.245.110.126.29.622.7 ibm042663313.554.010.026.59.621.4 ibm095174613.853.010.226.89.821.4 ibm138150814.647.310.323.69.719.3 ibm1515824415.152.810.526.59.920.6 Midrange thermal via densities produce Midrange thermal via densities produce 47.1% lower maximum temperatures 47.1% lower maximum temperatures 28.3% lower average temperatures 28.3% lower average temperatures

28. 28 Results Benchmark Circuit Thermal Via Regions T ave T max Run Time (sec) K ave % thermal via struct34.98.5%11.435.03.9 biomed50.19.2%10.924.118.2 ibm0157.114.1%10.126.219.1 ibm0451.612.7%10.126.543.1 ibm0951.112.6%10.326.861.5 ibm1359.814.8%10.323.6134.0 ibm1545.911.3%10.826.5191.5 Same maximum temperatures as with midrange via densities Same maximum temperatures as with midrange via densities 1.8% higher average temperatures 1.8% higher average temperatures 11.9% thermal via density in thermal via regions (1.2% in chip) 11.9% thermal via density in thermal via regions (1.2% in chip) 50.3% lower than the midrange value 50.3% lower than the midrange value

29. 29 Results Benchmark Circuit Thermal Via Regions T ave T max Run Time (sec) K ave % thermal via struct34.9 8.5% (-64.4%) 11.4 (4.6%) 35.0 (0.02%) 3.9 biomed50.19.2%10.924.118.2 ibm0157.114.1%10.126.219.1 ibm0451.612.7%10.126.543.1 ibm0951.112.6%10.326.861.5 ibm1359.814.8%10.323.6134.0 ibm1545.911.3%10.826.5191.5 Same maximum temperatures as with midrange via densities Same maximum temperatures as with midrange via densities 1.8% higher average temperatures 1.8% higher average temperatures 11.9% thermal via density in thermal via regions (1.2% in chip) 11.9% thermal via density in thermal via regions (1.2% in chip) 50.3% lower than the midrange value 50.3% lower than the midrange value

30. 30 Before Thermal Via Placement

31. 31 After Thermal Via Placement

32. 32 Conclusions Thermal vias have a greater effect in 3D ICs Thermal vias have a greater effect in 3D ICs Thermal via regions provide regularity Thermal via regions provide regularity Efficient iterative method Efficient iterative method Uses thermal gradients to adjust thermal conductivities Uses thermal gradients to adjust thermal conductivities Ideal maximum temperature Ideal maximum temperature Use lowered value as an objective Use lowered value as an objective Minimizes use of thermal vias Minimizes use of thermal vias Vias are put where they make the most impact Vias are put where they make the most impact Reduces thermal resistance on heat conduction paths Reduces thermal resistance on heat conduction paths