1. Mitigating the Performance Degradation due to Faults in Non-Architectural Structures Constantinos Kourouyiannis Veerle Desmet Nikolas Ladas Yiannakis Sazeides University of Cyprus Ghent University 6 th HiPEAC Industrial Workshop Paris, 26/11/2008

2. 6 th HiPEAC Industrial Workshop 2 Motivation  Technology scaling: Opportunities and Challenges  Reliability and computing tomorrow Failures will not be exceptional Various sources of failures  soft-errors, process-variation, wear-out, hardware and software bugs  Key challenge: provide correct operation with little or no performance degradation in the presence of faults with low- cost solutions

3. 6 th HiPEAC Industrial Workshop 3 Architectural vs Non-Architectural Faults  So far research mainly focused on correctness  Emphasis architectural structures, e.g. caches, registers, buses  However, faults can occur in non-architectural structures, e.g. predictor and replacement arrays  Faults in non-architectural structures may degrade performance

4. 6 th HiPEAC Industrial Workshop 4 Non-Architectural Faults: Why care?  Miss deadlines: unacceptable for real time applications  Non-architectural resources cover significant fraction of the active area of modern cores where temperature is higher more susceptible to wear-out and process variation faults  If architectural resources protected, with increasing fault frequency/chip eventually non-architectural resources will become a performance bottleneck

5. 6 th HiPEAC Industrial Workshop 5 This talk…  Quantifies performance implications of faults in a non- architectural array-structure, specifically a line predictor  Introduces and evaluates a simple detection scheme and repair technique to protect it against faults

6. 6 th HiPEAC Industrial Workshop 6 Outline  Fault Modeling Arrays background  Performance Implications of Faults in a line predictor  Detection - Repair Mechanisms  Results  Conclusions and Future Direction  Work in progress…

7. 6 th HiPEAC Industrial Workshop 7 Array Fault Modeling Key Parameters  Number of faults with increasing faults higher potential for performance degradation  Location of Faults frequently accessed entries more critical, output bit more serious  Fault Clustering Granularity/“radius” of faults  Model for each fault e.g. cell stuck-at-1 more critical if bits stored in the cell are biased towards zero

8. 6 th HiPEAC Industrial Workshop 8 Non-architectural Resources  Arrays line predictor branch direction predictor return-address-stack indirect jump predictor memory dependence prediction replacement arrays (various caches)...  Non-Arrays branch target address adder memory prefetch adder....

9. 6 th HiPEAC Industrial Workshop 9 Worst-case performance (cell faults) up to 27%

10. 6 th HiPEAC Industrial Workshop 10 Worst-case - Hit rate

11. 6 th HiPEAC Industrial Workshop 11 Detection and Repair  Possible to consider previously proposed techniques for architectural arrays  BUT detection and correction for non-architectural arrays does not have to be exact and provide full repair.  Sufficient to minimize the performance effects of faults  Our proposition: Address Remapping  Exploit non-uniformity of accesses Observed experimentally that few entries in the line-predictor are accessed. So, the remapping has a wide range of entries to go.

12. 6 th HiPEAC Industrial Workshop 12 (Sorted) Access Distributions for LP

13. 6 th HiPEAC Industrial Workshop 13 accessed cells accessed defective cells not accessed cells not accessed defective cells Original Access-Fault MapRotate accesses down by 1 row 1 instead of 3 accessed faulty cells Proposed Approach for Remapping

14. 6 th HiPEAC Industrial Workshop 14 accessed cells accessed defective cells not accessed cells not accessed defective cells Original Access-Fault Map Remap row accesses 1 instead of 3 accessed faulty cells Proposed Approach (for cell faults) 0 1 2 3 4 5 6 7 7 0 1 2 3 4 5 6

15. 6 th HiPEAC Industrial Workshop 15 Detection and Repair Scheme

16. 6 th HiPEAC Industrial Workshop 16 Index Remapping Unit 0 1 2 3 4 5 6 7 original index XOR 1 value decided from search engine 1 0 3 2 5 4 7 6 remapped index

17. 6 th HiPEAC Industrial Workshop 17 Remapping Search Engine 40 0 20 3 100 50 0 0 Access mapFault map 1 0 0 1 1 0 0 0

18. 6 th HiPEAC Industrial Workshop 18 Remapping Search Engine 40 0 20 3 100 50 0 0 Access mapFault map 1 0 0 1 1 0 0 0 Defective_accessed A =Σ i (Access map i * Fault map) = 40+3+100=143

19. 6 th HiPEAC Industrial Workshop 19 Remapping Search Engine 0 40 3 20 50 100 0 0 Remapped AccessesFault map 1 0 0 1 1 0 0 0 Best remapping = XOR 1(fewer defective accessed entries) Defective_accessed Β = Σ i (Access map i * Fault map) = 20+50=70

20. 6 th HiPEAC Industrial Workshop 20 Simulator  sim-alpha simulator  EV6 processor with 15 stage pipeline  Baseline configuration: No hard-fault, no remapping  SPEC CPU 2000 benchmarks – 100 M instructions Representative regions  We compare performance without and with remapping for random fault maps

21. 6 th HiPEAC Industrial Workshop 21 Random results without and with remapping

22. 6 th HiPEAC Industrial Workshop 22 Summary-Conclusions  Reliability should not be limited on correctness but also consider performance  Faults in non-architectural resources can degrade the performance of a processor and this may make them important to deal with  Proposed framework for detection and repair: Detects the case where there we have many defective accessed entries Finds the best possible remapping Applies the remapping  Remapping works very well in almost all cases

23. 6 th HiPEAC Industrial Workshop 23 Future Work  Experiments with other non-architectural structures, such as direction and indirect predictors and replacament arrays for I- cache, D-cache, TLB.  Applicability of ideas to architectural structures.

24. 6 th HiPEAC Industrial Workshop 24 Acknowledgments  Elli Demetriou and Costas Vrionis  Funding: University of Cyprus, Ghent University, SARC, HiPEAC, Intel

25. 6 th HiPEAC Industrial Workshop 25 Thanks!

26. 6 th HiPEAC Industrial Workshop 26 BACKUP SLIDES

27. 6 th HiPEAC Industrial Workshop 27 Processor Pipeline 27

28. 6 th HiPEAC Industrial Workshop 28 Line predictor structure 28

29. 6 th HiPEAC Industrial Workshop 29 Remapping Issues  Remapping overhead: time to find the best remapping has a penalty on performance, but this is acceptable because Remapping is performed every 100 K intervals Once the best remapping is found, the problem will be solved and there will be no need to remap again  Design Space Remapping function: XOR  Due to the fact that remapping is in the critical path, we use a simple remapping function to minimize the overhead in hardware

30. 6 th HiPEAC Industrial Workshop 30 Methodology: Performance Implications of Faults  Determine performance implications of faults in the LP and RAS for different scenarios  Worst-case Faults were injected on the most frequently used entries Most-used entry: provided most correct predictions for execution without faults  Average Impossible to do experimentally too many combinations Random : faults are injected at random entries

31. 6 th HiPEAC Industrial Workshop 31 Random results without and with remapping

32. 6 th HiPEAC Industrial Workshop 32 Faults and Arrays  Faults may occur in different parts of an array  Not practical to study faults at physical level

33. 6 th HiPEAC Industrial Workshop 33 Functional Faults and Array Logical View  Abstractions that ease study of faults  Fault locations: cell, input address, output data