1. The 68HC11 Microcontroller Minnesota State University, Mankato
Chapter 1: Introduction to 68HC11
The 68HC11 Microcontroller
Han-Way Huang
Minnesota State University, Mankato

2. Computer Hardware Organization
What is a computer?
Software
Hardware
Computer Hardware Organization
Control
unit
common bus
Arithmetic
logic
unit
memory
output
input
Registers
program
data
unit
unit
storage
storage
Figure 1.1 Computer hardware organization

3. The processor The microprocessor The Microcontroller
Registers -- storage locations in the processor
Arithmetic logic unit
Control unit
program counter keeps track of the address of the next instruction to be executed
status register flags the instruction execution result
The microprocessor
A processor implemented on a very large scale integration (VLSI) chip
Peripheral chips are needed to construct a product
The Microcontroller
The processor and peripheral functions implemented on one VLSI chip

4. Features of the 68HC11A8 microcontroller
- 8-bit CPU
- 256 bytes SRAM
- 512 bytes EEPROM
- 8 KB ROM
- 3 input capture channels
- 5 output compare functions
- one 8-bit pulse accumulator
- one serial communication interface (SCI)
- one serial peripheral interface (SPI)
- real-time interrupt (RTI) circuit
- 8-channel 8-bit A/D converter
- computer operate properly (COP) watchdog system

6. Examples of microcontroller applications
- Displays
- Printers
- Keyboards
- Modems
- Charge card phones
- Refrigerators
- Washing machines
- Microwave ovens
- Automobile engine fuel injection
- Fax machines
- Motor speed control
- etc.

7. Random-access memory (RAM): same amount of time
Semiconductor memory -
Random-access memory (RAM): same amount of time
is required to access any location on the same chip
Read-only memory (ROM): can only be read but not
written by the processor
Random-access memory
- Dynamic random-access memory (DRAM): periodic
refresh is required to maintain the contents of a DRAM chip
- Static random-access memory (SRAM): no periodic
refresh is required
Read-only memory
- Mask-programmed read-only memory (MROM):
programmed when being manufactured
- Programmable read-only memory (PROM): the memory
chip can be programmed by the end user

8. - Erasable programmable ROM (EPROM)
1. electrically programmable many times
2. erased by ultraviolet light (through a window)
3. erasable in bulk (whole chip in one erasure operation)
- Electrically erasable programmable ROM (EEPROM)
1. electrically programmable many times
2. electrically erasable many times
3. can be erased one location, one row, or whole chip in one operation
- Flash memory
3. can only be erased in bulk

9. Computer software
- Computer programs are known as software
- A program is a sequence of instructions
Machine instruction
- A sequence of binary digits which can be executed by the processor
- Hard to understand for human being
Assembly language
- Defined by assembly instructions
- An assembly instruction is a mnemonic representation of a machine
instruction
- Assembly programs must be translated before it can be executed --
translated by an assembler

10. High-level language
- Syntax of a high-level language is similar to English
- A translator is required to translate the program written in a
high-level language -- done by a compiler
Source code
- A program written in assembly or high-level language
Object code
- The output of an assembler or compiler

12. Memory Addressing Memory consists of addressable locations
A memory location has 2 components: address and contents
address
contents
Data transfer between CPU and memory involves address
bus and data bus
address bus lines
CPU
memory
data bus lines
Figure 1.5 Data transfer between CPU and memory

13. 68HC11 addressing modes
Table 1.1 Prefix for number representation
Base
Prefix
binary
octal
decimal
hexadecimal % @
nothing* $
*Note: Some assemblers use &
Operands needed in an instruction are specified by one of the 6
addressing modes
Immediate mode
The actual operand is contained in the byte or bytes immediately following the
instruction opcode
LDAA #22
ADDA
LDD #1000

14. Direct mode ADDA $10 SUBA $20 LDD $30 Extended mode LDAA $1000
A one-byte value is used as the address of a memory operand (located in on-chip SRAM)
ADDA $10
SUBA $20
LDD $30
Extended mode
A two-byte value is used as the address of a memory operand
LDAA $1000
LDX $1000
ADDD $1030
Indexed mode
The sum of one of the index registers and an 8-bit value is used as the address of a
memory operand
ADDA 10,X
LDAA 3,Y

15. Inherent mode ABA INCB INX Relative mode ... BEQ there ADDA #10
- Operands are implied by the instruction
- No address information is needed
ABA
INCB
INX
Relative mode
- Used in branch instructions to specify the branch target
- Specified using either a 16-bit value or a label (preferred)
...
BEQ there
ADDA #10
there DECB

16. A Sample of 68HC11 Instructions
The LOAD instructions
A group of instructions that place a value or copy the contents of a memory
location (or locations) into a register
LDAA <opr>
LDAB <opr>
LDD <opr>
LDX <opr>
LDY <opr>
LDS <opr>
<opr> can be immediate, direct, extended, or index mode
Examples
LDAA $10
LDX #$1000

17. The ADD instruction ABA ABX ABY ADDA <opr> ADDB <opr>
A group of instructions perform addition operation
ABA
ABX
ABY
ADDA <opr>
ADDB <opr>
ADDD <opr>
ADCA <opr>
ADCB <opr>
<opr> is specified using immediate, direct, extended, or index mode
Examples.
ADDA #10
ADDA $20
ADDD $30

18. SBCA <opr> ; A  [A] - <opr> - C flag
The SUB instruction
A group of instructions that perform the subtract operation
SBA
SUBA <opr>
SUBB <opr>
SUBD <opr>
SBCA <opr> ; A  [A] - <opr> - C flag
SBCB <opr> ; A  [B] - <opr> - C flag
<opr> can be immediate, direct, extended, or index mode
Examples
SUBA #10
SUBA $10
SUBA 0,X
SUBD 10,X

19. <addr> can be direct, extended, or index mode Examples: STAA $20
The STORE instruction
A group of instructions that store the contents of a register into
a memory location or memory locations
STAA <addr>
STAB <addr>
STD <addr>
STX <addr>
STY <addr>
STS <addr>
<addr> can be direct, extended, or index mode
Examples:
STAA $20
STAA 10,X
STD $10
STD $1000
STD 0,X

20. The 68HC11 Machine Code
A 68HC11 instruction consists of 1 to 2 bytes of opcode and 0 to 3 bytes of
operand information
Examples
Machine instructions
Assembly instruction (in hex format)
LDAA # D
STAA $
ADDA $ B 02
STAA $
INY

21. Decoding machine language instructions
Procedure
Step 1 Compare the first one or two bytes with the opcode table to identify the
corresponding assembly mnemonic and format.
Step 2 Identify the operand bytes after the opcode field.
Step 3 Write down the corresponding assembly instruction.
Step 4 Repeat step 1 to 3 until the machine code file is exhausted.
A sample of machine codes and assembly instruction format
machine code assembly instruction format
01 NOP
86 LDAA IMM
96 LDAA DIR
C6 LDAB IMM
D6 LDAB DIR
CC LDD IMM
DC LDD DIR
8B ADDA IMM
9B ADDA DIR
CB ADDB IMM

22. machine code assembly instruction format
DB ADDB DIR
C3 ADDD IMM
D3 ADDD DIR
97 STAA DIR
D7 STAB DIR
DD STD DIR
Example. Disassemble the following machine code to its corresponding assembly
instructions. B
Solution:
The disassembly process starts from the leftmost byte. We next look up
the machine code table to see which instruction it corresponds to.
Instruction 1.
Step 1. The first byte 96 corresponds to the instruction LDAA DIR.
Step 2. The second byte, 30, is the direct address.
Step 3. Therefore, the first instruction is LDAA $30.

23. Instruction 2.
Step 1. The third byte (8B) corresponds to the instruction ADDA IMM.
Step 2. The immediate value is 07.
Step 3. Therefore, the second instruction is ADDA $07.
Instruction 3.
Step 1. The fifth byte (97) corresponds to the instruction STAA DIR.
Step 2. The DIR address is the next byte 30.
Step 3. Therefore, the third instruction is STAA $30.
Instruction 4.
Step 1. The seventh byte (96) corresponds to the instruction LDAA DIR.
Step 2. The DIR value is the next byte 31.
Step 3. Therefore, the four instruction is LDAA $31.

24. machine code assembly instruction format
01 NOP
86 LDAA IMM
96 LDAA DIR
C6 LDAB IMM
D6 LDAB DIR
CC LDD IMM
DC LDD DIR
8B ADDA IMM
9B ADDA DIR
CB ADDB IMM
DB ADDB DIR
C3 ADDD IMM
D3 ADDD DIR
97 STAA DIR
D7 STAB DIR
DD STD DIR

25. The 68HC11 Instruction Execution Cycle
- Perform a sequence of read cycles to fetch instruction opcode byte and address
information.
- Optionally perform read cycle(s) required to fetch the memory operand.
- Perform the operation specified by the opcode.
- Optionally write back the result to a register or a memory location.
- Consider the following 3 instructions
Assembly instruction Memory location Opcode
LDAA $2000 $C000 B
ADAA $3000 $C003 BB 30 00
STAA $2000 $C006 B

26. Instruction LDAA $2000
Step 1. Place the value in PC on the address bus with a request to read the contents of that
location.
Step 2. The opcode byte $B6 at $C000 is returned to the CPU and PC is incremented by 1.

27. Step 3. CPU performs two read cycles to obtain the extended address $2000 from locations
$C001 and $C002. At the end the value of PC is incremented to $C003

28. Step 4. The CPU performs another read to get the contents of the memory location at
$2000, which is $19. The value $19 will be loaded into accumulator A.