1. Carrier mobility enhancement in strained silicon germanium channels
SiNANO Workshop
Carrier mobility enhancement in strained silicon germanium channels
David Leadley University of Warwick

2. Collaborators Warwick IMEC SINANO partners KTH, Udine, Chalmers, AMO
Tim Grasby, Andy Dobbie, Chris Beer, Jon Parsons, Evan Parker, Terry Whall
IMEC
Gareth Nicholas, Marc Meuris, M Heyns, P Zimmerman, Matty Caymax, ++
SINANO partners
KTH, Udine, Chalmers, AMO

3. Why is mobility still critical ?
High mobility - light mass and minimal scattering
ITRS – long term years
By 2020, Lg=5nm, Vdd=0.7V
Mobility enhancement factor of 1.04 each node
Ballistic enhancement factor x2
Double gate structures – light doping

4. Why add Ge? ADVANTAGES BUT… Smaller bandgap Lighter hole mass
Strain – splits bands and reduces scattering
BUT…
Native oxide no good
Band-to-band tunnelling

5. Pseudomorphic Si0.64Ge0.36 on Si
Mobility doubled

6. Nicholas et al, Electronics Letters 41, 20052074
Impact Ionisation
Reduced impact ionisation for SiGe, despite higher mobility
Nicholas et al, Electronics Letters 41,

7. High-k gated SiGe Deposited HfO2
Si cap – oxidises to thin SiO2 interlayer
Metal
HfO2
SiO2
SiGe Si
Lowest EOT 12Å
< 1nm

8. Metal gate/HfO2 gate stack development for Si(cap)/Si0.8Ge0.2 channel
Interface state density (W gate)
Gate leakage
Warwick, AMO, Chalmers

9. High-k/metal gated Si0.8Ge0.2 surface p-channel devices
enhancements beating Intel (IEDM 2004)
KTH, Warwick, Chalmers, AMO

10. KTH, Warwick, Chalmers, AMO
Effective Mobility
Best SiGe (25%) devices show mobility enhancement over silicon control
Mobility degradation compared to universal – interface roughness and Coulomb scattering important
KTH, Warwick, Chalmers, AMO

11. HOT SiGe Hybrid Orientation Technology
n on (100), p on (110) in Si, Yang et al. IEDM 2003
in Si, no variation with orientation for long channels, but <110> best for short channels, Saito et al VLSI 2006
50% enhanced Idsat for SiGe (110) over Si (100), 3.3x for mobility, Liu et al VLSI 2006
(110) substrate
[001]
[110]
(100) substrate
[011]

12. Novel p-channel/substrate orientations
= 3.2 nm
… enhancement beating Liu et al (VLSI Symp 2006)
KTH, Warwick, Chalmers, AMO

13. PMOS fabricated with Lg ~125 nm
Unstrained Ge pMOS
High performance Ge pMOS devices using a Si-compatible process flow
Zimmerman et al. IEDM 2006
4nm HfO2
2μm Ge on Si substrate
12Å EOT, TDD cm-2
PMOS fabricated with Lg ~125 nm
IMEC

14. Unstrained Ge Ge
+ anneal Si
IMEC

15. Uniformity restored after anneal
Nit spread 0.2-8x1012cm-2
affects Ids, gm and Vt
Uniformity restored after anneal
IMEC

16. Thinner EOT? Starts to leak when too thin !Si
Starts to leak when too thin !
Mobility increase with thinner HfO2
less charge trapping
Ragnarsson et al. IEEE TED 53, 1657 ( 2006)
IMEC

17. Mobility in unstrained Ge
μ > 300 cm2/Vs
Correction required for Rsd in short channel devices Lg<0.25μm
IMEC

18. Investigating trapped charge
Dit varies across wafer x1012cm-2
Warwick, IMEC

19. Interface charge density
Extract Dit in 3 ways at 300K:
from Vt – average all energies
subthreshold slope – specific energy
charge pumping
Interface charge density
Warwick, IMEC

20. Mobility modelling at 4K
At low T, with confinement only have one HH subband.
Fit using ni and D as parameters ...
Warwick, IMEC

21. Modelled 4K mobility ni agrees with values from Dit
Annealed
As grown
ni agrees with values from Dit
Δ decreases after anneal from 0.6nm to 0.5nm, hence μSR increases by 35%
μ300K must also depend on surface roughness
Warwick, IMEC

22. Strain tuning buffers Strained-Si by local strain now in production
Si1-yGey virtual substrates for global strain
y~0.2 for s-Si
y~0.5 for s-Si1-xGex
y~0.8 for s-Ge
Need low TDD and zero pile-up

23. Terrace Graded VS – better than industrial quality
20% Ge
XTEM
TDD ≤ 105cm-2, PUD=0
10x10um2 AFM image indicating RMS roughness 1.5nm
Warwick, LETI, Jeulich

24. State-of-the-art sSi electron mobility from TG-VSs
strain 0.6 – 1.1%
State of the art
F. Driussi et al., ULIS 2007
Warwick, Udine, KTH

25. sGe global platform - 80% terrace grade
TDD=3x105/cm-2, PUD = 0, RMS ≈ 8nm
Warwick, FZ-Jeulich, LETI

26. Novel thin VS for sGe Warwick
Seed layer
300nm Si0.2Ge0.8 Grade
Strained Ge
Si Sub
Strained Si
20x20 um2 AFM image. 1.3nm RMS, fully relaxed 80% platform
TDD ≈ 106/cm2 range
Warwick

27. Positive Vt due to gate workfunction
Strained Ge pMOS
150nm TiN
4nm ALD HfO2
Positive Vt due to gate workfunction
ASM, Warwick, IMEC

28. Record Ge mobility via CMOS process
Peak μ = 650 cm2/Vs
G. Nicholas et al., IEEE EDL 28, 825 (2007)
Warwick, IMEC

29. Further comments on s-Ge
Full band Monte Carlo calculations, incl. BTBT, SCE etc. show best prospect for pMOS …
… strained-Ge directly on Si ! Krishnamohan et al (Stanford) VLSI (2006)
For s-SiGe OI, Idsat enhancement in short channels exceeds μ increase in long channel. Tsutomu Tezuka et al. VLSI (2006)
nMOS still a problem for Ge … … but tensile strain Si0.1Ge0.9 on relaxed Ge promising.

30. Summary Addition of Ge improves mobility High-k makes Ge viable
Mobility enhancements relevant for nanometre scale devices

33. Terrace grading – new generation of virtual substrates
TDD ≈ 4 x 104 cm-2
PUD = 0
30%
Warwick

34. LG 30%
≈105 cm-2 TDD
Pile-up ≈1 cm-1

35. High stability sSi layers
Linear Grading
Relaxation (%)
Terrace Grading
Strained Si thickness (nm)
J. Parsons et al., ULIS 2007
Warwick, FZ-Jeulich

36. Extended Stacking Faults
Defect etch image of 20nm strained silicon layer
PVTEM image of 180nm strained silicon layer
J. Parsons et al., ULIS 2007
Warwick, FZ-Jeulich

37. Extended Stacking Faults
“Perfect” dislocation
Stacking fault
Trailing (30°) “partial” dislocation
Leading (90°) “Partial” dislocation
S-Si
SiGe

38. Stacking faults – effective misfit dislocation blockers?
Defect etch images of 30nm strained silicon layer
J. Parsons et al., ULIS 2007
Warwick, FZ-Jeulich

39. 50% terrace graded (for sSi)
TDD = 2x105 cm-2
PUD = 0
Warwick

40. ≈ 20% TG - slower growth (+sSi)
TDD = 4 x 104/cm2
PUD = 0

41. Schottky Barrier MOSFET- world best?
Tunnelling f(m*)
Thermionic
emmision
Measurement
Modelling
D.J. Pearman et al., IEEE Trans ED (accepted 2006)
UCL, Warwick, Glasgow