1. Hyper Status and Preliminary Testing of the New Hyper Bus Fault Detector CP Work done by CP section 10-12.2008 Based on Slides from Knud DAHLERUP-PETERSEN Architectural Design by Reiner DENZ Analysis by Zinur CHARIFOULLINE

2. ❖ Preliminary Bus Splice Quality Characterization ( Nano Ohm Meter Function) ❖ Voltage Signal Noise Reduction Integration Hierarchy ❖ Differential Analog Bandwidth: 0-200 Hz (tested at 1 kHz) ❖ 24bit ∑∆ ADC (modulator frequency: 32768 Hz) ❖ Hardware (in QPS) 24bit ∑∆ ADC integration period: 187 mS (5.35 Hz) ❖ Firmware (in QPS) moving rectangular integration: 18.9 S (101 samples) ❖ Software (in CCC) DC integration time: typically > 10 minutes (this is what counts!) ❖ Feasibility of nΩ Resolution ? ❖ Real Time Early Warning Bus Fault Detection ❖ Bus Inductance Compensation (94 µH) ❖ Feasibility of 300 µV Threshold ? Both functional aspects of the new bus fault detector have been tested:

3. Results from Measurements Performed on 27 Oct. at up to 1250 ADC DQQDC Detector Card now linked up to the WorldFip  and LHC Logging Strong Filtering, Sampling Time 187 ms, 100 points Sliding Average Post Treatment of Data with Labview  380 µV 1250 A 1 hour

4. Results from Measurements Performed on 27 Oct. Voltage during Ramping 1250 A 380 µV 4 A/s

5. Results from Measurements Performed on 27 Oct. at 1250 ADC Results from Ramping, Flat-Top and Ramp-down ±10 µV Real Time Noise Floor

6. Results from Measurements Performed on 27 Oct. at 1250 ADC with DQQDC Detector 100 nV 490 ± 90 pΩ 245 ± 45 pΩ / Splice Zero Closure = 20 nV ~ 1 hour integration / point

7. 7 Bus Voltage Selected DC Data 50 µV 375 µV 4 A/s 1 hour 94 µH 3500 Amp Ramp 3500 Amp Ramp 29 October

8. Results from Measurements Performed on 29 Oct. at 3500 ADC with DQQDC Detector 8 290 ± 50 pΩ / Splice 200 nV 580 ± 100 pΩ Zero Closure = 50 nV 10 min - 1 hour integration / point

9. 9 500 nV 650 ± 29 pΩ Results from Measurements Performed on 30 Oct. at 5000 ADC with DQQDC Detector 325 ± 15 pΩ / Splice Zero Closure = 50 nV

10. Ramp [Amp] Resistance/Splice [pΩ]estimated statistical error [pΩ] 125024545 350029050 500032515 mean28728 Repeatability & Consistency Repeatability & Consistency Same Splice Different Ramps Different Days Can we measure better than 1 nΩ ? YES WE CAN !

11. 11 1 µV 1550 ± 340 pΩ Results from Measurements Performed on 30 Oct. at 5000 ADC with COMPENSATED DQQDC Detector 520 ± 110 pΩ / Splice

12. 671 ± 43 pΩ 335 ± 22 pΩ / Splice 500 nV Can we measure better than 1 nΩ ? YES WE CAN !

13. 13 97% Compensated Signal Residual = 10 µV out of 400 µV First Feeble Attempt at Compensation 4 A/s

14. Bus Voltage 375 µV Uncompensated Bus Signal Serious Attempt at Compensation

15. Can we have a detection threshold better than 300 µV ? YES WE CAN ! ±300 µV 4 A/s PC recapture ! Completely Compensated Bus Signal

16. Can we have a detection threshold better than 300 µV ? YES WE CAN ! ±20 µV

17. Conclusions from Preliminary Testing Signal noise is amazingly insensitive to cable routing. –This allows practical routing in the cable trays. Barring any unforeseen noise issues, sub nΩ resolution should be possible. A 300µV real time early warning threshold is practical. –But keep in mind that saturation at high field or magnetization at low field may spoil compensation slightly. –Some variation in splice resistance must be tolerated. –Some variation in electronic component noise must be tolerated. –And many unexplored and hence unforeseen noise sources may spoil and consume our threshold margin. (TGV, Bastille Day, etc.) –A healthy margin must be maintained, as false trips may keep the Higgs away. –Only after operational experience with the entire system will we know if the threshold really needs to be increased for stability or possibly could be decreased to provide added security. (The threshold needs to be secure but flexible.) YES WE CAN !