1. Quad 2-to-1 and Quad 4-to-1 Multiplexers Discussion D2.4 Example 7

2. Quad 2-to-1 Multiplexer

3. y <= ~s*a + s*b; may only AND bits of a STD_LOGIC_VECTOR of equal length.

4. sel: STD_LOGIC_VECTOR(3 downto 0); sel <= s & s & s & s; y <= (not sel and a) or (sel and b);

5. -- Example 7a: Quad 2-to-1 MUX using logic equations library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux24a is port( s : in STD_LOGIC; a : in STD_LOGIC_VECTOR(3 downto 0); b : in STD_LOGIC_VECTOR(3 downto 0); y : out STD_LOGIC_VECTOR(3 downto 0) ); end mux24a; architecture mux24a of mux24a is signal sel: STD_LOGIC_VECTOR(3 downto 0); begin sel <= s & s & s & s; y <= (not sel and a) or (sel and b); end mux24a;

6. -- Example 7b: Quad 2-to-1 MUX using if statement library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux24b is port( s : in STD_LOGIC; a : in STD_LOGIC_VECTOR(3 downto 0); b : in STD_LOGIC_VECTOR(3 downto 0); y : out STD_LOGIC_VECTOR(3 downto 0) ); end mux24b; architecture mux24b of mux24b is begin process(a, b, s) begin if s = '0' then y <= a; else y <= b; end if; end process; end mux24b;

7. Aldec Active-HDL Simulation

8. A Quad 4-to-1 MUX

9. -- Example 7c: Quad 4-to-1 MUX using with..select..when library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux44 is port( a : in STD_LOGIC_VECTOR(3 downto 0); b : in STD_LOGIC_VECTOR(3 downto 0); c : in STD_LOGIC_VECTOR(3 downto 0); d : in STD_LOGIC_VECTOR(3 downto 0); s : in STD_LOGIC_VECTOR(1 downto 0); y : out STD_LOGIC_VECTOR(3 downto 0) ); end mux44; architecture mux44 of mux44 is begin with s select y <= a when "00", b when "01", c when "10", d when others; end mux44; Note selected signal assignment statement

10. Aldec Active-HDL Simulation