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Published byPatrick Rudolf Lyons Modified over 9 years ago
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QUAD MODULE TESTING 18 th January 2013 Kate Doonan University of Glasgow
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Quad Module: 200μm ROC Chip ID 1 – no longer working due to accidental damage. Bonds will be checked Chip ID 3 – not working: no RX signal. Bonds will be checked. Chip ID 4 – not wire-bonded yet Chip ID 2 – Working: Tuned to 3200e and 1600e thresholds Working Chip 1
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Chip ID 2 Characterisation Biased to -100V at room temperature Module kept from heating by constant airflow from fan from the side Kept from light exposure using dark box Leakage current 50nA in complete darkness 2
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Chip ID 2: Tune to 3200e threshold Threshold tuned to 3200e Best result obtained through standard TDAC- FDAC-TDAC cycle during tuning 3
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Initial TDAC tune gave better result but ToT had to be tuned Taken sample of pixels here to make scan shorter Chip ID 2: Tune to 3200e threshold 4
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Low Noise: 116.4e. Sigma of 200e is considered acceptable Chip ID 2: Tune to 3200e threshold 5
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Log Y used to look in detail at noise Chip ID 2: Tune to 3200e threshold 6
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See chip is tuned to ToT ~8 @ ref. charge of 20ke Again, best result obtained through TDAC-FDAC-TDAC cycle Chip ID 2: Tune to 8ToT @ 3200e 7
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Initial FDAC tune gave good ToT but altered threshold value considerably Chip ID 2: Tune to 8ToT @ 3200e 8
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Noise Occupancy @ 3200e: 10 mill events Bias OFF 9 Mask produced for pixels with occupancy over 1,000
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Bias -100V Noise Occupancy @ 3200e: 10 mill events 10 Mask produced for pixels with occupancy over 1,000
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Bias OFF Some pixels exhibit crosstalk when sensor is unbiased Crosstalk @ 3200e Threshold 11
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Bias -100V Fewer pixels exhibiting crosstalk at -100V 12 Crosstalk @ 3200e Threshold
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A number of pixels are shown to be disconnected around the edges Will use ROOT macro to ascertain exact number of pixels that are disconnected 3200e Threshold Scan 0V – bump yield 13
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Zoom into 120e region Judging by eye, ~6,500 pixels exhibit noise around 120e giving a yield of ~25% disconnected pixels 3200e Threshold Scan 0V – bump yield 14
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Behaviour of Single Chip Noise plots of single chip (VTT Assembly 15) at threshold of 3200e: 0V 100V 15
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Threshold tuned to 1600e Some pixels remain tuned to threshold of 3200e Tuning down was very quickly done Chip ID 2: Tune to 1600e threshold 16
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Again, low noise: 133e Sigma <200e Chip ID 2: Tune to 1600e threshold 17
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Log Y used to look in detail at noise Chip ID 2: Tune to 1600e threshold 18
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ToT not perfect but in correct region. Could be improved with more fine-tuning. Chip ID 2: Tune to 8ToT @ 1600e 19
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Bias OFF Noise Occupancy @ 1600e 20 Mask produced for pixels with occupancy over 1,000
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Bias -100V Noise Occupancy @ 1600e 21 Mask produced for pixels with occupancy over 1,000
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Chip exhibits more crosstalk at this lower threshold Crosstalk @ 1600e Threshold 22
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No discernible peak around 120e Compare to biased assembly in next slide 1600e Threshold Scan 0V – bump yield 23
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1600e Threshold Scan 0V – bump yield 24
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Log Y used to look in detail at noise Pixels with highest noise values are on top in occupancy plot 1600e Threshold Scan 0V – bump yield 25
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Zoom into top rows of occupancy plot Noise in these pixels is >500e 1600e Threshold Scan 0V – bump yield 26
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Looking at SCURVES for a sample of pixels HOT PIXEL 1600e Threshold Scan 0V SCURVES Row 4, Column 14: 27
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Looking at SCURVES for a sample of pixels WELL-BEHAVED PIXEL 1600e Threshold Scan 0V SCURVES Row 261, Column 31: 28
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Looking at SCURVES for a sample of pixels SWITCHED-OFF/BROKEN PIXEL 1600e Threshold Scan 0V SCURVES Row 144, Column 13: 29
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Summary Chip 2 can be tuned to threshold of 3200e and 1600e and a ToT of 8 ~25% disconnected pixels In general, this assembly behaves as a single chip assembly Nothing to indicate otherwise 30
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Work yet to do … Fine-tuning of Chip 2 to threshold of 1600e/ToT=8 Use ROOT macro to find number of disconnected bumps on Chip 2 Set-up Sr90 scans – beta particles should penetrate to other side to be detected in PMT for triggering Try Am241 scans – HITOR not bonded and it is thought that this is needed for Am241 scans Wire-bonding of Chip 4 Tuning and characterisation of Chip 4 31
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