1. ITRS Emerging Logic Device working group George Bourianoff, Intel San Francisco, Ca July 10, 2011 April 10, 20112011 ERD Meeting Potsdam, Germany 1

2. Outline Overview Review transition Table Table 1 Table 2 Table 3 issues and observations 2

3. Overview Section organization and tables unchanged from previous edition New format for Transition table Some Technology Entries changed tables based on revised classification Several new Technology Entries from NRI Improved connection to ERM Connection to ERA still weak 3

4. 2011 Logic Transition Table 4

5. Transition table discussion Adds clarity – Unchanged entries – no comment – Dropped entries – easy to indicate reason – New entries – show up clearly – Holding entries for possible future inclusion- easy to indicate None in current table

6. 2011 Table 1 MOSFETs Extending MOSFETs to the End of the roadmap 6

7. Table 1 discussion Si CMOS reference – which device? Demonstrated CNTFET circuit speed increased from 220Hz to 56 MHz Demonstrated τ s for GNRFET increased from 26 GHz to 300 GHz Significant progress on Ge/oxide interface to improve N channel mobility, short channel, N type Ge MOSFET elusive, lower resistance contacts needed Tunnel FETs: many demonstrations of SS 10 5. Low I on remains problem

8. 2001 Table II –Charge based beyond CMOS

9. Table II discussion Si CMOS reference – which device? MEM density increased from ~10 3 /cm 2 to >10 8 /cm 2 Atomic Switch: 10 11 cycles demonstrated, basic device physics still not understood IMOS entry reflects new fundamental understanding – Switch speed limited by “multiplication delay”. However, very steep ST slopes achieved ~2 mV/decade (but at high voltage) Spin MOSFET : major progress from use of high quality, full Haussler alloy, half metal source/drains MottFET: Very fast phase transition <<ps observed

10. Table ERD7C Alternative information processing devices

11. Table III Discussion 4 new devices from NRI – Excitonic FET –ultra steep SS, room temperature operation problem – Spin Torque Majority Gate – 2 types, simulations only – All Spin Logic- simulations only NML: Clocking from fields generated by a metal line clad, ferromagnetic line, metastable magnetic configurations to reduce energy Ferroelectric negative Cg: Transferred from table 2 and modified: - SS <60mV/ decade demonstrated, single crystal ferroelectric oxide on Si an issue

12. Issues and observations

13. # Decisions Made 1. Memory: ♦ Put Vertical MOSFET in the Memory Section. 2. Logic: ♦ Leave n-channel Ge and InP MOSFETs and p-channel GaSb MOSFETs in ERD/ERM ♦ The Tunnel FET should remain in the main Logic Tables and Section. ♦ Nanowire FET stays in ERD/ERM. ♦ Remove molecular from Logic Section – does not meet criteria ♦ Add MOTT-FET to the Logic Section ♦ Remove SET or move SET to the MtM Section ♦ Keep InP and Ge n-channel and GaSb p-channel MOSFETs in the Logic Section ♦ Add devices from NRI that meet the selection criteria ♦ Do not include Vertical MOSFET in Logic; keep/put in Memory Section. ♦ Change “Collective Spin Wave? to “Spin Wave”. ♦ Logic Working Group is: Shamik (Nanowires), Adrian (Tunnel FET),??(InP, Ge, GaSb), Jeff Welser (NRI Devices added), Jeff Kitun? ♦ Include the Spin Torque Majority Gate. ♦ Keep the Atomic Switch in Logic Tables (corrected Feb. 17, 2011) April 10, 20112011 ERD Meeting Potsdam, Germany13 DONE