1. 6 th International Conference on Position Sensitive Detectors, Leicester 11/09/2002 Yu.Gornushkin gornushk@sbgpcs26.in2p3.fr - 1 - Outline: G. Claus, C. Colledani, G. Deptuch, M.Deveaux, W. Dulinski, A.Gay, Yu. Gornushkin, A.Himmi, Ch. Hu-Guo, I.Valin, and M. Winter IReS and LEPSI, IN2P3/ULP, 23, rue du Loess BP 23 (BP 20), F-67037 Strasbourg, France Tracking Performances and Radiation Tolerance of Monolithic Active Pixel Sensors. Principle of operation of CMOS sensorsPrinciple of operation of CMOS sensors Resent results with first small prototypes (resolution, rad.tolerance)Resent results with first small prototypes (resolution, rad.tolerance) Performances of 1 st real scale prototype (3.5 cm 2, 1 million pixels)Performances of 1 st real scale prototype (3.5 cm 2, 1 million pixels) Status of 1 st prototype with column parallel readout andStatus of 1 st prototype with column parallel readout and integrated CDS integrated CDS SummarySummary

2. 6 th International Conference on Position Sensitive Detectors, Leicester 11/09/2002 Yu.Gornushkin gornushk@sbgpcs26.in2p3.fr - 2 - Idea and principle of operation  Twin-tub (double well) CMOS process with moderately doped epitaxial layer providing long minority carrier lifetime Charge is generated in epitaxial layer (low doping): Q ~80e - -h/  m Charge is collected through thermal diffusion by n-well/p-epi diode No depletion potential applied Potential barriers at layer interfaces confine the charge – improving collection efficiency Charge-Voltage conversion on pixel The device can be fabricated using a standard CMOS process, P-type low resistivity Si  only NMOS transistors allowed CMOS MAPS are replacing CCDs in visible light applications (still and video cameras, web-cameras, cell phones) – low power consumption, cheap!  To use them also for m.i.p. detection In Strasbourg (IReS-LEPSI) since 1999

3. 6 th International Conference on Position Sensitive Detectors, Leicester 11/09/2002 Yu.Gornushkin gornushk@sbgpcs26.in2p3.fr - 3 - First Prototypes - Summary of Performances First Prototypes - Summary of Performances MIMOSA I die size 3.6 × 4.2 mm 2 Device internal architecture e.g. MIMOSA II Examples of pixel layouts M I: 20 × 20 µm 2 High performances in m.i.p. detection established: S/N~30, e >99%,  sp ~1.5-2 m m

4. 6 th International Conference on Position Sensitive Detectors, Leicester 11/09/2002 Yu.Gornushkin gornushk@sbgpcs26.in2p3.fr - 4 - Recent MIMOSA-1 results Real particle clusters overlapped and combined distribution approximated by charge distribution function fot 2 hits. Hits are well separated at distances > 30  m. The spatial resolution as a function of ADC-bit encoding ( real signals “digitized” offline): even with 3-4 bits s ~2-3 m m

5. 6 th International Conference on Position Sensitive Detectors, Leicester 11/09/2002 Yu.Gornushkin gornushk@sbgpcs26.in2p3.fr - 5 - MIMOSA-4 test results: 0.35 mm AMS process without epitaxial layer but with low doping (resistivity) substrate Observed performances with 120 GeV/c p- at CERN-SPS: Detection efficiency ~99.7% S/N ~30 but charge spread is wider Spatial resolution ~4 m m (20 m m pitch) Technology without epitaxial layer seems worth investigating and optimizing p-substrate process (~10 15 cm -3 ) 4 arrays 64x64 pixels - pixel pitch 20x20 mm 2 diode (nwell/p-epi) size 2x2 m m 2 - 1.8 fF serial analogue readout - max. clock freq.: 20 MHz die size 3.7x3.8 mm 2 technology 3M+2P power supply 3.3 V radiation tolerant transistor design new structures of charge sensing elements: - charge spill-gate, - current mode pixel, - self-biasing diodes

6. 6 th International Conference on Position Sensitive Detectors, Leicester 11/09/2002 Yu.Gornushkin gornushk@sbgpcs26.in2p3.fr - 6 - Neutron radiation tolerance Noise as a function of fluence: Observed charge loss as a function of fluence: Charge loss is observed only for fluences >10 11 n/cm 2 what is 2 orders of magnitude more than it is expected for TESLA! Chips irradiated with neutron sources at JINR and CEA-Saclay reactors were tested with Fe 55 X-ray source.

7. 6 th International Conference on Position Sensitive Detectors, Leicester 11/09/2002 Yu.Gornushkin gornushk@sbgpcs26.in2p3.fr - 7 - MIMOSA 5: big chip - simple quick start solution  AMS 0.6 µm process with ~14 µm epitaxial layer  analogue readout - with hardware processing (CDS, pedestal subtraction, S/N analysis, sparsification on-line)  stitching: coarse - 100 µm + scribeline, option:precise – 1  m  Lot of 6”wafers 44 kEuro 19.4 mm 17.35 mm One chip ~10 6 pixels of 17x17 m 2 One chip ~10 6 pixels of 17x17  m 2

8. 6 th International Conference on Position Sensitive Detectors, Leicester 11/09/2002 Yu.Gornushkin gornushk@sbgpcs26.in2p3.fr - 8 - MIMOSA-5 tests The chip (4 matrices of 512  512 pixels (17x17  m 2 ) etched down to 120  m was exposed to 120 GeV/c  - beam at CERN-SPS The same process as MIMOSA-1  the same performances expected? Preliminary results: Noise mean ENC 20.7 e - Seed pixel S/N 23 Detection efficiency e ~99.3%, s sp ~1.7  m, s sp ~1.7  m, s gain  2- 3% s gain  2- 3% close to those of MIMOSA-1 Noise larger than in case of MIMOSA-1 (different serial r.o.architecture – double source follower stage) Epitaxy layer ~14 m m  charge ~1000e -

9. 6 th International Conference on Position Sensitive Detectors, Leicester 11/09/2002 Yu.Gornushkin gornushk@sbgpcs26.in2p3.fr - 9 - MIMOSA-5 response to inclined tracks (very preliminary): Total charge follows cos -1 ( q ) S/N grows as well (saturation observed due to geometrical effect at large angles) MIMOSA-5 tests will continue in October 2002 at CERN-PS

10. 6 th International Conference on Position Sensitive Detectors, Leicester 11/09/2002 Yu.Gornushkin gornushk@sbgpcs26.in2p3.fr - 10 - MIMOSA-6 – first sensor with integrated signal processing 0.35 MIETEC technology (same as MIMOSA-2) IReS-LEPSI/DAPNIA collaboration 24 column readout in parallel 128 pixels per column 5MHz effective readout frequency (30MHz clock, 6 clock cycles/pixel) Amplification (x5.5), Correlated Double Sampling on pixel Discriminators integrated on chip periphery (1 per column) Power dissipation ~500 mW per column Pixel layout: 28x28 m m 2 Chips are expected back from foundry this days. Test results - by the end of 2002. Charge storage capacitors 29 transitstors AC coupling capacitor Matrix of 128x30 pixels Discriminators Chip layout:

11. 6 th International Conference on Position Sensitive Detectors, Leicester 11/09/2002 Yu.Gornushkin gornushk@sbgpcs26.in2p3.fr - 11 - Summary: o The good performance of CMOS MAPS in charge particle detection has been succesfully established with 4 generations of small scale prototypes: e  99%,  sp ~1.5-2.5  m, S/N~30,  2hit ~30  m o Tolerance to neutrons exceeds TESLA requirements by more than 2 orders of magnitude! o Preliminary results from MIMOSA-5 tests indicate that these performances are reproducible with real size detectors (~3.5 cm 2, 120  m thin) o First chip with integrated signal processing functions (CDS+A+D) is coming back from fabrication soon  tests in October 2002 o R&D programme on CMOS MAPS TESLA Vertex Detector in a collaboration of 10 labs in F-UK-CH-NL-D+… is under way.