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Assessing Chip-Level Impact of Double Patterning Lithography Kwangok Jeong *, Andrew B. Kahng *,**, and Rasit O. Topaloglu ***

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Presentation on theme: "Assessing Chip-Level Impact of Double Patterning Lithography Kwangok Jeong *, Andrew B. Kahng *,**, and Rasit O. Topaloglu ***"— Presentation transcript:

1 Assessing Chip-Level Impact of Double Patterning Lithography Kwangok Jeong *, Andrew B. Kahng *,**, and Rasit O. Topaloglu *** http://vlsicad.ucsd.edu/ * ECE Dept., UC San Diego ** CSE Dept., UC San Diego *** GlobalFoundries, Inc.

2 (2)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Outline Double Patterning Lithography (DPL) Traditional Interconnect Analysis Additional Variability in DPL Misalignment in Double Patterning Analysis in Different DPL Options Experiments Conclusion

3 (3)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Outline Double Patterning Lithography (DPL) Traditional Interconnect Analysis Additional Variability in DPL Misalignment in Double Patterning Analysis in Different DPL Options Experiments Conclusion

4 (4)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Double Patterning Lithography (DPL) Pattern-doubling: ‘2X-resolution’ lithography with ‘1X-resolution’ equipment Taxonomy Resist type: positive /negative Methods: double exposure (DE) / double patterning (DP) / spacer double patterning (SDP) Printed feature: line / space Target layer Resist 1 st Exposure 2 nd Exposure Mask1 Mask2 Target layer Resist Mask 1X-resolution 1X 2X-resolution 1X

5 (5)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Traditional Interconnect Analysis Designers use capacitance tables from foundries 2D/3D field solver with variations  Capacitance tables Major sources of variation: Metal/dielectric density- dependent systematic variation Random process variation Results of variation Width (W) variation Metal height (H) variation Dielectric thickness (D) variation, etc. Traditional interconnect variation analysis 1. for (i = -3 ; i  3 ; i=i+1) { 2. for (j = -3 ; j  3 ; j=j+1) { 3. for (k = -3 ; k  3 ; k=k+1) { 4. W=W nom + i  W  5. H= H nom + j  H  6. D= D nom + k  D  7. run field solver over parameterized structure}}} 8. Find nominal and worst-case capacitance M+1 M-1 M W H D

6 (6)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Additional Variability in DPL Overlay error Causes: mask misalignment material stress-impacted deformations litho-/etch-impacted topography lens aberration, etc. Impacts on DPL Width variation Space (or pitch) variation  Capacitance variation Alignment metric Indirect: Two DPL masks aligned to a reference layer Error: Direct: Second DPL mask aligned to the first DPL mask Error: S S S S Indirect Alignment (IA) Cc Cg Direct Alignment (DA)

7 (7)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Outline Double Patterning Lithography (DPL) Traditional Interconnect Analysis Additional Variability in DPL Misalignment in Double Patterning Analysis in Different DPL Options Experiments Conclusion

8 (8)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Misalignment in Positive DE/DP 1212 1 WW S S mask2 Positive photoresist Dielectric Space on one side increases Space on the other side decreases Required design of experiments foreach S  (-3  ~ 3  ) mask1  shift by + S/2 mask2  shift by – S/2 end mask1 After exposure + etch Cu filling (misaligned to left)

9 (9)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Misalignment in Negative DE/DP 1212 1 W’’W’ SS PP S/2 mask1 mask2 (misaligned to left) Negative photoresist Dielectric After exposure + etch After filling Cu Width of one increases Width of the other decreases Required design of experiments foreach S  (-3  ~ 3  ) mask1  change W by + S  shift by S/2 mask2  change W by – S  shift by S/2 end

10 (10)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Spacer Thickness Variation in Positive SDP Dielectric After exposure + etch (kind of) Positive photoresist Primary patterns Spacers (act as if masks) After filling Cu Cu Width and space change Required design of experiments foreach S  (-3  ~ 3  ) mask1  change W by 0 mask2  change W by + S end 1212 1 WW’’ PP SS

11 (11)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Spacer Thickness Variation in Negative SDP 1212 1 W’ P’’P’ SS Primary patterns Dielectric After exposure + etch After filling Cu Spacers (act as if masks) (kind of ) Negative photoresist Cu Width and space change Required design of experiments foreach S  (-3  ~ 3  ) mask1  change W by + S/2  shift by + S/4 mask2  change W by + S/2  shift by – S/4 end

12 (12)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Outline Double Patterning Lithography (DPL) Traditional Interconnect Analysis Misalignment in Double Patterning Analysis in Different DPL Options Experiments Conclusion

13 (13)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 PhotoresistProcessAlignment Experiments: Scenarios We examine impact of misalignment and linewidth variation across various DPL options Parallel 5-Interconnect Structure (TCAD tool) Interconnects in a full-chip (Signoff RCX) Indirect Direct Positive Negative DE DP SDP Direct Positive Negative DE DP SDP

14 (14)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 TCAD-Based BEOL Analysis Results Capacitance variation due to misalignment in DE/DP IA shows larger variation than DA Negative resist processes have larger variation Capacitance variation in different DPL options SDP has larger variation Negative resist processes have larger variation Capacitance (aF/um)

15 (15)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Design-Level Analysis - Flow Overlay-aware extraction flow 1. Design GDS TOP.GDS Initial GDS AES core with NanGate 45nm Tech. 2. Split GDS Base GDS Sub-GDS1 Sub-GDS2 DPL layers Non-DPL layers 3. Pattern Decomposition Sub-GDS1-1 Sub-GDS1-2 Sub-GDS2-1 Sub-GDS2-2 ILP-based min cost coloring (Kahng et al. ICCAD08) Coloring and Splitting 4. Shift and Merge (Cadence Virtuoso) Shifting and Merging TOP.GDS 5. Resize and Extraction (Synopsys Hercules, Star-RCXT) Resizing

16 (16)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Overlay error can cause more than +/- 10% capacitance variation within a die, for all DPL options  Large on-chip variation  Increase of timing optimization difficulty Capacitance Variation (%) Design-Level Capacitance Variation M2 M3 M4M5

17 (17)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 A net having maximum crosstalk delay (17um long) SDP shows more sensitivity  tighten overlay spec P-DE/DP shows least sensitivity  lessen overlay spec Maximum Crosstalk-Induced Delay P-DE/DP (Space on one side) N-DE/DP (Width) P-SDP (Spaces on both sides) N-SDP (Space & width) M4 |S||S|/2 M2 M4M2 M4 w/o metal fillw/ metal fill

18 (18)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Total Negative Slack Variation SDP, especially for lower layer (smaller feature), shows more sensitivity  tighter overlay spec TNS Variation (%)

19 (19)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Outline Double Patterning Lithography (DPL) Traditional Interconnect Analysis Misalignment in Double Patterning Analysis in Different DPL Options Experiments Conclusion

20 (20)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Summary of Observations Overlay error with indirect alignment (IA) results in higher capacitance variations compared to direct alignment (DA) Capacitance can vary > 10% due to misalignment  Large OCV  increase timing optimization difficulty Timing can be degraded significantly, e.g., > 10% worse TNS P-DE/DP may be the most favorable option for BEOL DPL With the same 3  overlay control, the variation in P-DE/DP is 50% of N-DE/DP or P-SDP, and 25% of N-SDP   Overlay control spec for P-DE/DP can be relaxed by 2X compared to others

21 (21)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Conclusion and Ongoing Work We provide a variational interconnect analysis framework for double patterning lithography We analyze mechanisms of interconnect variations due to misalignment and spacer thickness variation in DPL We provide both interconnect and design-level RC- extraction framework reflecting interconnect variation in a 45nm DPL process We compare the impact of overlay error in different DPL options Ongoing work Development of timing analysis and optimization methodology considering interconnect variation in DPL Incorporation of statistical techniques to target pessimism reduction

22 Thank You!

23 (23)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Impact of Misalignment on FEOL Standard cell decomposition Experimental setup 10nm 3  misalignment is assumed between layers Design of experiments (all permutation: 3*3*3*3 = 81 cases) P1: -10nm (L) / 0nm (C) / +10nm (R) P2: -10nm (L) / 0nm (C) / +10nm (R) M: -10nm (L) / 0nm (C) / +10nm (R) C: -10nm (L) / 0nm (C) / +0nm (R) Original MP1P2C BASE

24 (24)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Experimental Results on FEOL Flow Impact of misalignment on cell delay is negligibly small (< 2%) Capacitance variation due to misalignment << gate capacitance Measured Delay Variation (%) P1P2M C LCR L L L0.911.190.89 C 1.150.87 R 1.130.83 C L0.060.230.45 C0.040.190.4 R0.040.170.38 R L-1.45-0.68-0.64 C-1.47-0.72-0.66 R-1.47-0.74-0.7 C L L0.721.020.7 C 0.980.68 R 0.960.64 C L-0.150.040.23 C-0.1500.21 R-0.17-0.020.17 R L-1.68-0.89-0.87 C-1.68-0.94-0.89 R-1.7-0.96-0.91 R L L0.510.850.51 C0.490.810.49 R0.470.790.47 C L-0.38-0.150.02 C-0.38-0.190 R-0.4-0.21-0.02 R L-1.94-1.11-1.09 C-1.94-1.15-1.11 R-1.96-1.15-1.13 Tr-level RC-Extraction STAR-RCXT Circuit Simulation HSPICE

25 (25)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 DPL Options Double ExposureDouble PatterningSpacer-DP Photoresist Printed Feature mask positive resist negative resist After exposure & etch Dielectric After Cu filling (a) Positive-tone(b) Negative-tone Cu interconnect mask positive resist After exposure & etch Dielectric (a) Spaces (Trench-First)(b) Lines Cu interconnect Poly Target layer Resist Hardmask Buffer oxide Hardmask Target layer 1 st Litho-etch Spacer formationOxide depo. CMP Spacer removal 2 nd etch Mask Target layer Resist Hardmask 1 st Litho-etch 2 nd Litho-etch Mask1 Mask2 Target layer Resist 1 st Exposure 2 nd Exposure Mask1 Mask2

26 (26)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Mask Coloring and Layout Examples in DPL Mechanism of misalignment-induced variation (a) DE and DP Process (b) SDP Process 1 2 3 4 5 6 1 2 3 4 5 6 1 4 5 2 3 6 Original patterns Original patterns Coloring Patterns 1 Patterns 2 Coloring Spacer formation (Large spacer) Trim & repair (dark gray) SS Narrow space W 1 2 3 4 5 6 W” Dummy for pattern 6 1 4 5 2 3 6 Spacer (gray) a b

27 (27)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Design-Level Analysis - DOE Design of Experiments for DE/DP with DA 1.foreach layer  { M2, M3, M4, M5 } 2. decompose layer into layer mask1 and layer mask2 3. foreach S  { -3  /2, -2  /2, -  /2, 0,  /2, 2  /2, 3  /2} 4. shift layer mask1 by S 5. shift layer mask2 by –S 6. end 7. layer  layer mask1 + layer mask2 8. foreach  W  { -3  /2, -2  /2, -  /2, 0,  /2, 2  /2, 3  /2} 9. resize layer by  W 10. end 11. merge with other layers 12. RC-Extraction and Timing Analysis 13. end

28 (28)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Impact on Capacitance Variation Total interconnect capacitance: maximum  C(%) Among top 20% high capacitance nets Impact of overlay < impact of  width Sum of capacitance in the most critical path Critical path has short interconnects  impact of BEOL variation significantly reduces Impact of overlay < impact of  width -3  +3  MinAvgMaxMinAvgMax Overlay-7.7%1.4%9.2%-7.3%1.4%9.7% Width-22.2%4.7%7.1%-3.6%5.3%28.6% Interconnect onlyInterconnect + Gate MinMaxMinMax Overlay-0.08%0.47%-0.04%0.25% Width-1.87%2.59%-0.99%1.38%

29 (29)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Impact on Crosstalk-Induced Delay Maximum coupling induced delay change PrimeTime-SI (Synopsys) is used to find a net that is mostly affected due to crosstalk Temporal/functional filtering is performed Selected net structure A net with relatively small length (~17um) can have >10%  delay changes due to overlay error Cc (pF)Cg (pF)  Delay @Min@Max@Min@MaxMinMax Overlay1.8421.8631.0891.053-0.47%13.1% Width1.8401.9061.0891.120-0.82%15.4% M2 segment: 1.604um M3 segment: 0.78um M4 segment: 14.788um Capacitance when  Delay is minimum Capacitance when  Delay is maximum

30 (30)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Impact on Timing Longest path and total negative slack (TNS) Impact of overlay << impact of  width Longest path delay changes negligibly However, overall timing (TNS) can change significantly Longest path  delay  TNS MinMaxMinMax Overlay-0.06%0.98%3.2%3.8% Width-1.22%2.00%-34.3%49.4% Total Negative Slack (ns)

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