Download presentation
Presentation is loading. Please wait.
Published byRalph McCoy Modified over 9 years ago
1
CRKIT R5 Clock Architecture WINLAB – Rutgers University June 13, 2013 Khanh Le
2
Zedboard Zynq System Clock Overview PSPL 33.333MHz ref clock (IC18, PS_CLK) F7 4 programmable PL clocks 100MHz ref clock (IC17, GCLK) Y9 For portability, use the 100MHz reference clock for PL section (will require one PLL) ref_clk_out (RF ref clock ~30MHz) B19, B20 L18, L19 dac_clk_in (dac ref clock) dac_clk_out (dac source synchronous clock) E19, E20 D18, C19 adc_clk_in (adc source synchronous clock)
3
Zynq PS System Clocks ARM PLL 33.333MHz PS_CLK I/O PLL DDR PLL Mux 6-bit prog. divider 6-bit prog. divider 6-bit prog. divider Mux Clock Ratio Generator cpu_6x4x cpu_3x2x cpu_2x cpu_1x CPU, SCU OCM AXI Interconnect ddr_3x ddr_2x Sync Async 6-bit prog. divider I/O Peripherals USB, Ethernet SDIO, SMC SPI, QSPI, UART CAN, I2C PL PL Clocks Check the clocks on EDK tool !! (REVISIT)
4
RF Interface dac_data_out[15:0] dac_clk_out dac_frame_out (unused) Not used for word-level, only for Byte- or Nibble-level AD9122 DAC AD9548 Clock Sync AD9523 Clock Gen AD9643 ADC dac_clk_in ref_clk_out(~30MHz) Jitter clean up adc_data_in[13:0] adc_clk_in adc_or_in I Q 1 0 LVDS CMT PLL ODDR (SAME_EDGE Mode) clock feedback DAC Interface RF Reference Clock ADC Interface I2C Interface @tx_clk CMT MMCM CTL REG Programmable ref. clock (ug472) 100MHz Rx Baseband D1 D2 Q D1 D2 Q By default, +Rising edge = I +Falling edge = Q +Twos complement Anti-aliasing filter cut-off @125MHz -> Nyquist sampling rate @250MHz I Q Q1 Q2 D IDDR (SAME_EDGE_PIPELINED Mode) CMT MMCM @125MHz clock feedback scl sdata I2C -> SPI PCORE INT REG @125MHz Sampling Rate Down Conversion Clock domain crossing. Must support fractional synchronization e.g. 125MHz -> 20MHz Tx Baseband Sampling Rate Up Conversion By default, +Rising edge = I +Falling edge = Q +Twos complement + ~1ns skew between data and DCO (DCO delay vs data) @prog_rx_clk For fractional clock divider CLKOUT1 CLKOUT0 @100MHz sys_clk M=3, D=2, O1=5 M=3, D=2, O0=1.5 CLKOUT1 CLKOUT0 NOT NEEDED (no clock deskew) CLKOUT0 CLKOUT1 @prog_tx_clk REVISIT : do we need interpolation in the framework ? Or use the DAC for interpolation ? Answer – interpolation within Framework. (Up/Down conversion not critical at this point)
5
ODDR Timing
6
IDDR Timing
7
DAC Timing DAC Register Map Default Data bus sampling point is nominally 350ps after each edge of DCI signal, with uncertainty of +/- 300 ps. Data interface timing can be verified using the Sample Error Detection (SED) circuitry (reg 0x07, 0x67-0x73). Reference : AD9122_DAC.pdf
8
ADC Timing ADC Register Map Interleaved IQ channels : Chan A = I Chan B = Q Reference : AD9643_ADC.pdf ~1ns skew between data and DCO For parallel interleaved mode
9
Xilinx 7-series Clock Management Tile (CMT) Mixed-mode clock manager Phased-lock loop, subset of MMCM functions 1 CMT = 1 MMCM + 1 PLL Zynq Z-7020 PL clock resources : + 4 CMTs e.g. 4 MMCMs & 4 PLLs + 4 programmable clocks from PS CLKIN only Applications : + clock network deskew + frequency synthesis + jitter reduction
10
CMT - MMCM Programming port (ug472 + xapp888) Integer counter Independent clock control Fractional counter With Fclkin = 100MHz, M=1, D=1 : Integer divide : O0 = 1 : Fout = 100MHz O1 = 2 : Fout = 50MHz O2 = 3 : Fout = 33.33MHz O3 = 4 : Fout = 25MHz O4 = 5 : Fout = 20MHz O5 = 6 : Fout = 16.66MHz Fout = 80MHz, then O0 = Fclkin/Fout = 100/80 = 10/8 = 1.25 (fractional divide). Fout = 30MHz, O0 = 100/30 = 3.3333… Alternative, M=3, D=2, O1=5 : CLKOUT1 = 30MHz (rf ref clock) M=3, D=2, O0=1.5 : CLKOUT0 = 100MHz (system clock) With Fclkin = 125MHz (ADC sync clock), M=1, D=1 : Fout = 80MHz, O0 = 125/80 = 1.5625 Fout = 20MHz, O0 = 125/20 = 6.25 Attributes : M = CLKFBOUT_MULT_F D = DIVCLK_DIVIDE O = CLKOUT_DIVIDE (ug472, page 79)
11
CMT - PLL Integer only counter Programming port Attributes : M = CLKFBOUT_MULT_F D = DIVCLK_DIVIDE O = CLKOUT_DIVIDE
12
MMCM and PLL Use Models (ug472, page 87) Requires two BUFGs Requires only one BUFG + jitter filtering + frequency synthesis + no phase requirement between Fin and Fout Off-chip compensation Input buffers must be in same bank. Use COREGEN to get additional settings information.
13
Clock Network Deskew Restrictions Restrictions for feedback : F in F out F FB Example 1 : F in = 166MHz, D = 1, M = 6, O = 2 F VCO = M x F FB = M x (F IN / D) F VCO = 6 x 166MHz = 996MHz and F OUT = F VCO / O = 996MHz / 2 = 498 MHz 1 6 2 F in F out F FB 30 4 Example 2 : F in = 66.66MHz, D = 2, M = 30, O = 4 F VCO = M x F FB = M x (F IN / D) = 30 x (66.66MHz / 2) = 999.9MHz ~ 1000MHz and F OUT = F VCO / O = 1000MHz / 4 = 250 MHz 2
14
ADC Network Deskew Restrictions for feedback : F in F out0 -> rcv baseband clock F FB Example 1 : Given F in = 125MHz, wants F OUT0 = 20MHz, F OUT1 = 125MHz What are the appropriate values for D, M, O0 and O1 ? (note, O0 = fraction, O1 = integer) F OUT0 = F VCO / O0 = 20MHz -> O0 = F VCO / F OUT0 F OUT1 = F VCO / O1 = 125MHz -> O1 = F VCO / F OUT1 F VCO ? F VCO = M x F FB = M x (F IN / D) +Assuming D = 1, M = 2 => F VCO = 2 x F IN = 2 x 125 = 250 MHz And O0 = F VCO / F OUT0 = 250 / 20 = 12.5 O1 = F VCO / F OUT1 = 250 / 125 = 2 +Assuming D = 1, M = 4 => F VCO = 4 x F IN = 4 x 125 = 500 MHz And O0 = F VCO / F OUT0 = 500 / 20 = 25 O1 = F VCO / F OUT1 = 500 / 125 = 4 ? ? ? F out1 -> adc interface clock e.g. decimation… Example 2 : Given F in = 125MHz, wants F OUT0 = 80MHz, F OUT1 = 125MHz +Assuming D = 1, M = 2 => F VCO = 2 x F IN = 2 x 125 = 250 MHz And, O0 = F VCO / F OUT0 = 250 / 80 = 3.125 O1 = F VCO / F OUT1 = 250 / 125 = 2 +Assuming D = 1, M = 4 (doubles) => F VCO = 2 x F IN = 4 x 125 = 500 MHz And, O0 = F VCO / F OUT0 = 500 / 80 = 6.25 (doubles) O1 = F VCO / F OUT1 = 500 / 125 = 4 (doubles) ?
15
Clock Distribution e.g. Zedboard Zynq how many APP can be supported ?
16
Interpolation/Decimation – Rational Sampling Rate Converters SAVE FOR LATER ! NOT CRITICAL AT THIS POINT
17
Clock Domain Abstraction Layers MOVE TO SEPARATE DESIGN DOCUMENT !
Similar presentations
© 2025 SlidePlayer.com. Inc.
All rights reserved.