1. CMOS Camera System-on-a-Chip
ECE Senior Project
CMOS Camera
System-on-a-Chip
FIRST PAGE

2. TEAM MEMBERS Anil Kumar Angana Sheth Saurabh Desai George Moran
Jason Moffa
Takashi Ishihara
ADVISOR: Dr. Brita Olson
SECOND PAGE

3. CMOS Camera System-on-a-Chip
A normal camera uses film to save the image that hits its lens.
We are designing a chip that saves the image digitally by sensing the amount of light or image that each one of its pixel sees.
The image consists of 128 by 128 pixels: there are total pixels.
ANIL INTRO 1

4. PROJECT DIAGRAM
128 x128
ANIL INTRO 2

5. Design Goals
ANGANA INTRO 1

6. Establishing a Chip Design Infrastructure
Learning VLSI Design
Learning VLSI Design Tools and Chip Design Process
Establishing a Chip Design Flow at CPP
Configuring tools
ANGANA INTRO 2

7. Progress Calculations/Analysis: Component Development:
Floor Planning Conversion Gain
Parasitics /Loading Noise
Component Development:
Design Optimization, Simulation with loading, Port to new environment
Decoder primitive Anti-blooming Circuitry
Decoder Bus Driver Row driver: Row RST & SEL Driver
Anti-blooming Circuitry Amplifier Bias Circuitry
Pixel Analog Signal Chain Sample & Hold Circuit
ANGANA INTRO 3

8. Progress (cont.) Chip Level Design: In progress: Pixel Array schematic
7-bit decoder
Analog Signal Chain with Correlated Double Sampling
ANGANA INTRO 4

9. Accomplished Tasks Floor Planning 7 Bit Decoder
Anti Blooming Circuitry

10. FLOOR PLANNING Pitch = 150um 16 pads 16 pads 3mm 136*12um 3mm
The floor plan estimates the area of major
units in the chip and defines their relative
placements.
The floor plan is essential to determine
whether a proposed design will fit in the chip area budgeted and to estimate wiring lengths and wiring congestion, so an initial floor plan should be prepared as soon as the logic is loosely defined.
Pitch: It is a distance between two pads.
Pads: They are wired to the pins on the chip package. They are for the I/O connection on the chip
128*128
Imager
3mm
16 pads
136*12um
3mm
4 AMI 0.5um Tiny Chips
Packaging : 150um pad pitch
Pixels : 12um pitch

11. APS Architecture Row Decoder: Selects row for readout. Column Decoder:V E S
Row Decoder:
Selects row for readout.
Column Decoder:
Controls readout of
Pixels In given row.
128*128
PIXEL ARRAY
Row[i]
27=128
128
A decoder is a Combinational circuit, when enabled, produces one of 2n minterms or maxterms at the output based on the input Combinations.
READOUT CIRCUITS
128
COLUMN DECODER
27=128

12. Decoder Implementation
Row-add<0:6>
Row-add<0:6>
Selects row 0 1
Selects row 1
A 7 input nand gate based implementation results in a compact and regular realization reducing development time and cost.
The chip that we are designing has 128*128 pixels so the decoder consists of 128 of 7 input nand gates.

13. Decoder Design Requirements
Master Clock = 20MHz
Trise/Fall requirements are relaxed.
In our design Trise/Fall times are 50% of clock.
Trise/Fall = ½(1/20MHz)
= 25ns

14. Schematic of 7-input nand gate
PMOS Operational W/L
= (W min/L min to 7W min/L min)
NMOS Operational W/L
= W min/7L min
Both NMOS & PMOS are
minimum sized transistor
(W=1.05um, L=0.7um)
W/L eff PMOS : 1.05/0.7
W/L eff NMOS : 1/7(1.05/0.7)

15. Simulation for fall time when W = 1.05um

16. Simulation for rise time when W = 1.05um

17. Rise / Fall Time Table Rise Time Fall Time W = 1.05um 1.46ns 2.709ns
L = 0.7um
Better Trise/Fall times results due to reduced W
of PMOS transistor.
Reduced W of transistor results in
Reduction of power consumption
Reduction in substrate noise
Reduction in input capacitance – Reduces chip area,
power, & noise.

18. Anti Blooming Circuitry
Reduces charge buildup in pixels due to excessive illumination
Prevents flow of excess charge into neighboring pixels.
It does this by redirecting the excess current into the anti-blooming drain when the photodiode is too full.
Without anti blooming circuitry imaging artifacts will happen.

19. Anti Blooming Circuit Operation
Vdd
RST = 5V
RST_LO = 1V
VTH = 0.7V
RST 5v
RST_LO = 1V
Integration
Normal Imaging Condition:
When RST signal is applied FD is around 2.8V and after integration
of light it becomes 1.8V.
(Vgs < VTH) = 1 – 1.8 < 0.7 - Transistor Off
Bright Light:
Due to bright light FD decreases to 0.3V
(Vgs >= VTH) = 1 – 0.3 >= 0.7 – Transistor on and excess carriers removed.

20. Anti Blooming Circuitry
Final stage of row driver
Anti blooming circuitry

21. 7 BIT INPUT SIGNAL DECODER DRIVER
ANIL SLIDE 1

22. Schematics
Driver (4x8x) Driving a load of 64, CMOS N and P transistors.
ANIL SLIDE 2

23. Simulations Rise Time ~ 6% Fall time ~ 5%
Approximate time is 1 nano second to drive signal.
ANIL SLIDE 3

24. VALUES GIVEN
W = 1.05uM
L = 0.7uM
VDD = 3.3v

25. SCHEMATIC V5 V4 V0
VDD

26. SCHEMATIC RESULT

27. SYMBOL FOR THE AND GATE
ROW [i]
RST[i]
RST

28. Accomplished Tasks
1. Determine Resistive and Capacitive Parasitic Loading (Caused by dimension of the pixel Array)
2. Row Driver Design
-Determine best combination for Drivers
-Rise and Fall Times
-Reset Driver
-Select Driver
3. Simulations using PSPICE
4. Implementation of Design using Cadence (LINUX)
GEORGE SLIDE 1

29. Chip Schematic
GEORGE SLIDE 2

30. Overview of Row Driver
SEL
SEL[i]
ROW[i]
GEORGE SLIDE 3

31. Parasitic Loading Determination of load resistor:
Determination of Capacitive load:
GEORGE SLIDE 4

32. The Row Driver
GEORGE SLIDE 5

33. The Row Driver (cont.)
GEORGE SLIDE 6

34. Simulations Summarized
Table 1: Rise and Fall Times for Inverter driving 128 transistors
(using 102,400,402,600ns; Vdd=3.3V; Cload= 41.4fF)
Table 2: Rise and Fall times for inverters driving inv_8x
GEORGE SLIDE 7

35. Schematics Two Drivers (4x_8x) Driving 128 CMOSN transistors
GEORGE SLIDE 8

36. Simulations
Rise/Fall Times
GEORGE SLIDE 9

37. Row Select Driver Design
Three Drivers (1x_4x_8x) Driving 128 CMOSN transistors
GEORGE SLIDE 10

38. Row Select Driver Simulation with Loading
Rise/Fall Times
GEORGE SLIDE 11

39. Row Reset Driver Design
Introduction of two different power supply levels
GEORGE SLIDE 12

40. Simulations
Rise/Fall Times
GEORGE SLIDE 13

41. General Chip Layout

42. Pixel & Timing Diagrams

43. Current Mirror Circuit To Bias Pixel SF
“Large” gate widths and lengths used
Good threshold matching
gm reduced
Current Equation

44. Determining Initial Condition For Sample & Hold Capacitor
Pixel
Sample & Hold Capacitor
Bias
Optimize RST signal due to Body Effect

45. The Body Effect
Source ≠Body
Modified threshold voltage:

46. Initial Condition for Sample & Hold Capacitor

47. Determining Time to Discharge Sample & Hold Capacitor Within 0
Determining Time to Discharge Sample & Hold Capacitor Within 0.1% Accuracy
VFD initial condition: V = 1.8V

48. Transient Response of Pixel Discharge

49. Determining time to charge sample & hold capacitor Within 0
Determining time to charge sample & hold capacitor Within 0.1% Accuracy

50. Transient Response of Pixel Charge

51. Accomplishments Designing output driver
Determining the conversion gain
Designing the pixel array

52. Output Driver
Pixel Array
ADC
Analog Sig. Chain
Parasitic Capacitance

53. Output Driver Operation
CL = 8pF
Vout
Vin
DV = 1V
Slewing
(25%)
Settling
(75%)
Step function
Ttot = 100% = .5msec
Slewing: small sig. Analysis not appropriate
Settling: transistors in saturation

54. Schematic

55. Settling Vin DV = 1V Amplifier transfer function: Output:
Settling accuracy
Vin
DV = 1V
Step function:

56. Tfall output Driver (35uA)

57. Trise output Driver (35uA)

58. Slewing and Settling

59. Conversion Gain Cm Cm(1-A) C(total) = Cfd + Cm(1-A) V = Q/C
Miller Effect Cm
Cm(1-A)
C(total) = Cfd + Cm(1-A)
V = Q/C
C.G.= Vout/Number of Electrons
= q/C(total)

60. Conversion Gain Gate Source (3) W 4λ 4λ W (2) (1) Source (1): Cj(W*4λ)
(2): Csw(W+2*4λ)
(3): Cswg*W
Cfd = Cj(W*4λ)+ Csw(W+2*4λ)+Cswg*W
=1.19fF

61. Conversion Gain Vout 0.8 0.9 0.9 C(total)
C(total) = Cfd+Cm(1-A) = 1.19fF
Input: C.G.= q/C(total) = 134uV/electron
Output: C.G.= (0.8)(0.9)(0.9)(134u)
= 87.1uV/electron

62. CHIP PROCESS
ANIL CONCLUSION 1

63. Remaining Tasks Component development Chip Level Schematic Development
Optimization of Analog Signal chain with CDS
Chip Level Schematic Development
Completion of Decoder
Pad Ring
Assembly of final chip schematic
“Full” Chip Simulations
Layout
ANGANA INTRO 5

64. Acknowledgments
ANGANA CONCLUSION 1