1. NI @ ECE.UTAustin.Edu Prof. Brian L. Evans
Prof. Brian L. Evans
Dept. of Electrical and Computer Engineering
The University of Texas at Austin, Austin, Texas USA
Contributions by Profs. Francis Bostick, Bruce Buckman, Robert Heath, Archie Holmes, Jon Valvano. Additional contributions by Vishal Monga, Zukang Shen, Ahmet Toker, and Ian Wong, also UT Austin.

2. Outline
Introduction
Real-Time Digital Signal Processing (DSP) Lab Course
Wireless Communications Lab Course (Prof. Robert Heath)
Prototyping Ad-Hoc Networks (Prof. Robert Heath)
Conclusion

3. 10 ECE faculty positions open
Introduction
ECE Department at UT Austin
62 tenured and tenure-track faculty (expanding to 75)
1500 undergraduate and 600 graduate students
LabVIEW license for ECE predates 1996
May be installed on any ECE machine or any ECE student machine
Use of NI products in ECE courses predates 1996
Required junior-level electronics lab course
LabVIEW coupled with NI data acquisition system to measure time and frequency responses of devices
10 ECE faculty positions open

4. Introduction The Wild West of course numbering at UT Austin
First digit indicates the number of credits
Middle digit of 0 means first-year undergraduate course
Middle digit of 1 means second-year undergraduate course
Middle digit of 2-7 means upper division course
Middle digit of 8-9 means graduate course
I just work here …
EE 302 Introduction to Electrical Engineering
Required for first-year first-semester ECE students
Use NI ELVIS workstation for all analog circuits labs
Saves significant amount of lab space
Prof. Archie Holmes

5. EE 438 Electronics I – Lecture Component
Junior-level required course for both majors
In-class demonstrations using NI ELVIS
Demonstrate performance of a variety of electronic circuits
Project ELVS board using a document camera
Switch to simulated measuring instruments to analyze performance
In-class demonstrations using NI Electronics Workbench
Often coupled with ELVIS demonstration
Similar approach for EE 338K Electronics II
Junior-level elective for both majors
Prof. Francis Bostick

6. EE 438 Electronics I – Lab Component
Objectives of junior-level required course for both majors
Make time- & frequency-domain measurements on electronic circuits
Utilize measurements with predictions from circuit simulation software (like PSPICE or MultiSIM) to troubleshoot circuits
Automated stimulus/response measurements
Diode rectifiers and amplifiers based on MOSFETs & BJTs
Using NI digital acquisition hardware controlled by suite of LabVIEW Express VIs developed for course
Entire lab content delivered to students via the Web
Prof. Bruce Buckman

7. EE 362K Intro to Auto. Control
Required senior-level course for BSEE majors
Uses LabVIEW to design feedback control systems
System identification of system to be controlled
Students interactively add/delete poles/zeros from a transfer function until it agrees with time and frequency measurements of the plant
Analog controller design to tailor closed-loop system
Students interactively add/delete poles/zeros in controller to achieve target closed-loop system performance in time and frequency
Digital controller design for implementation
Students interactively modify controller to fix problems as sampling frequency lowered toward realistic final value
Prof. Bruce Buckman

8. EE 464 Senior Design Project
Required senior-level course for all majors
Students work individually or in teams of two
Sample projects using LabVIEW
Shaun Dubuque and Richard Lam, “Vital Signs Monitor”
Steven Geymer and Matt Dione, “Infrared Eye Tracking System with Distributed Control”
Stephen Pun, "Discrete Multitone Modulation Modem Testbed“
Altamash Janjua and Umar Chohan, "OFDM Transmitter Based on the Upcoming IEEE d Standard“
Abdelaziz Skiredj, "Quantifying Tradeoffs in Adaptive Modulation Methods for IEEE a Wireless Communication Systems"

9. Selected Graduate Courses
EE 382C-9 Embedded Software Systems
System-level modeling and simulation (breadth)
Dataflow modeling, scheduling, and synthesis (depth)
LabVIEW is homogeneous dynamically-scheduled dataflow model
EE 385J-17 Biomedical Instrumentation II
Lab 1. Analog/Digital Noise Analysis w/ LabVIEW
Lab 2. Heart Sounds w/ LabVIEW
Lab 5. Embedded System Project (LabVIEW or 9S12C32)  
Prof. Brian Evans
Prof. Jonathan Valvano

10. Real-Time DSP Course: Overview
Objectives of undergraduate elective class
Build intuition for signal processing concepts
Explore signal quality vs. complexity tradeoffs in design
Translate DSP concepts into real-time software
Lecture: breadth (three hours/week)
Laboratory: depth (three hours/week)
Deliver voiceband transceiver using TI DSP processors/tools
Test/validate implementation using NI LabVIEW and rack equipment
“Design is the science of tradeoffs” (Prof. Yale Patt, UT)
Over 600 served since 1997

11. Real-Time DSP Course: Show Me The Money
Embedded system demand: volume, volume, …
400 Million units/year: automobiles, PCs, cell phones
30 Million units/year: ADSL modems and printers
How much should an embedded processor cost?
Source: CEA Market Reseach. Data for 2004 calendar year.

12. Real-Time DSP Course: Which Processor?
How many digital signal processors are in a PC?
Digital signal processor worldwide revenue
$6.1B ‘00, $4.5B ‘01, $4.9B ‘02, $6.1B ‘03, $8.0B ‘04
Estimated annual growth of 23% until 2008
43% TI, 14% Freescale, 14% Agere, 9% Analog Dev (‘02)
Fixed-point DSPs for high-volume products
More than 90% of digital signal processors sold are fixed-point
Floating–point DSPs used for initial real-time fixed-point prototype
Floating-point DSP resurgence in professional and car audio products
Program floating-point TI TMS320C6700 DSP in C
Revenue figures from Forward Concepts (

13. Real-Time DSP Course: Textbooks
C. R. Johnson, Jr., and W. A. Sethares, Telecommunication Breakdown, PH, 2004
“Just the facts” about single-carrier transceiver design
Matlab examples
CD supplement featuring Rick Johnson on drums
S. A. Tretter, Comm. System Design using DSP Algorithms with Lab Experiments for the TMS320C6701 & TMS320C6711, Kluwer, 2003
Assumes DSP theory and algorithms
Assumes access to C6000 reference manuals
Errata/code:
Bill Sethares (Wisconsin)
Steven Tretter (Maryland)

14. Real-Time DSP Course: Where’s Rick?
Rick Johnson (Cornell)

15. Real-Time DSP Course: QAM Transmitter
LabVIEW reference design/demo by Zukang Shen (UT Austin)
Lab 4 Rate Control
Lab 6 QAM Encoder
Lab 2 Passband Signal
Lab 3 Tx Filters

16. Real-Time DSP Course: QAM Transmitter
Control
panel
QAM
passband
signal
Eye diagram
LabVIEW demo by Zukang Shen (UT Austin)

17. Real-Time DSP Course: QAM Transmitter
square root raised cosine, roll-off = 0.75, SNR = 
passband signal, 1200 bps mode
passband signal, 2400 bps mode
raised cosine, roll-off = 1, SNR = 30 dB

18. Real-Time DSP Course: Lab 2. Sine Wave Gen
Ways to generate sinusoids on chip
Function call
Lookup table
Difference equation
Ways to send data off chip
Polling data transmit register
Software interrupts
Direct memory access (DMA) transfers
Expected outcomes are to understand
Signal quality vs. implementation complexity tradeoffs
Interrupt mechanisms, DMA transfers, and codec operation

19. Real-Time DSP Course: Lab 2. Sine Wave Gen
Evaluation procedure
Validate sine wave frequency on scope
Test subset of 14 sampling rates on board
Method 1 with interrupt priorities
Method 1 with different DMA initialization(s)
Old School HP 60 MHz Digital Storage Oscilloscope
New School
C6701 DSP
LabVIEW DSP
Test Integration Toolkit 2.0
Code Composer Studio 2.2

20. Real-Time DSP Course: Lab 3. Digital Filters
Implement digital linear time-invariant filters
FIR filter: convolution in C and assembly
IIR Filter: direct form and cascade of biquads, both in C
Expected outcomes are to understand
Speedups from convolution assembly routine vs. C
Quantization effects on IIR filter stability
FIR vs. IIR: how to decide which one to use
Filter design gotcha: polynomial inflation
Polynomial deflation (rooting) reliable in floating-point
Polynomial inflation (expansion) may degrade roots
Keep native form computed by filter design algorithm 
x[k]
y[k]
Unit Delay
1/2
1/8
y[k-1]
y[k-2]

21. Real-Time DSP Course: Lab 3. Digital Filters
IIR filter design for implementation
Butterworth/Chebyshev filters special cases of elliptic
Minimum order not always most efficient
In classical designs, poles sensitive to perturbation
Quality factor measures sensitivity of pole pair to oscillation: Q  [ ½ ,  ) where Q = ½ dampens and Q =  oscillates
Elliptic analog lowpass IIR filter example [Evans 1999] Q
poles
zeros
1.7 ±j
0.0±j
61.0 ±j
0.0±j Q
poles
zeros
0.68 ±j ±j
10.00 ±j ±j
optimized
classical

22. Real-Time DSP Course: Lab 3. Digital Filters
Evaluation procedure
Sweep filters with sinusoids to construct magnitude/phase responses
Manually using test equipment, or
Automatically by LabVIEW DSP Test Integration Toolkit
Validate cut-off frequency, roll-off factor…
FIR: Compare execution times
C without compiler optimizations
C with compiler optimizations
C callable assembly language routine
IIR: Compute execution times
Labs 4-7 not described for sake of time
Test Equipment
Agilent Function Generator
HP 60 MHz Digital Storage Oscilloscope
Spectrum Analyzer

23. Wireless Comm. Lab: Overview
A typical digital communication system
Physical world
Transmitter
Source
Channel
Analog
Source
Modulation
Coding
Coding
Processing
Channel
Propagation
Medium
Source
Channel
De- modulation
Analog
Sink
Decoding
Decoding
Processing
Receiver
Digital
Analog
Slide by Prof. Robert W. Heath, Jr., UT Austin,

24. Wireless Comm. Lab: A DSP Approach
Decompose block diagram into functional units
Inputs
System
Outputs
h[n]
h(t)
time
time
time
time
Slide by Prof. Robert W. Heath, Jr., UT Austin,

25. Wireless Comm. Lab: Premises
Learning analog communication e.g. AM/FM are no longer essential (think vacuum tubes)
A digital communication system can be abstracted as a discrete-time system
Concepts from signals and systems can be used to understand the complete wireless system
Experimental approach to wireless builds intuition on system design
Slide by Prof. Robert W. Heath, Jr., UT Austin,

26. Wireless Comm. Lab: Course Topics
DSP models for communication systems
Sampling, up/downconversion, baseband vs. passband
Power spectrum, bandwidth, and pulse-shaping
Basics of digital communication
QAM modulation and demodulation
Maximum likelihood (ML) detection
Dealing with impairments
Channel modeling, estimation and equalization
Sample timing, carrier frequency offset estimation
Orthogonal frequency division multiplexing (OFDM)
Initial offering in Spring 2005
Slide by Prof. Robert W. Heath, Jr., UT Austin,

27. Wireless Comm. Lab: One Lab Station
Transmitter
PXI-5421
PXI-5610
Channel
Modulation
D/A
RF Up
Source
Coding
Channel
Sink
Decoding
Demod
A/D
RF Down
PXI-5620
PXI-5600
SMA
MXI-3
Dell PC with LabVIEW software
PXI Chassis
Receiver
Slide by Prof. Robert W. Heath, Jr., UT Austin,

28. Wireless Comm. Lab: One Lab Station
Slide by Prof. Robert W. Heath, Jr., UT Austin,

29. Prototyping Ad Hoc Networks: Introduction
Ad hoc networks are loose collections of nodes
Important for military applications
Applications to in-home networking
Prototyping requires physical & network software
Slide by Prof. Robert W. Heath, Jr., UT Austin,

30. Prototyping Ad Hoc Networks: Description
Radio
RF transceiver uses TI IEEE a/b/g radio
ADC / DAC using NI 5620 and NI 5421
Physical layer
In LabVIEW on embedded PC in PXI chassis
PHY / MAC interface
Gigabit Ethernet
Medium access control
Implemented in Linux on dedicated PC
Networking (packet routing, etc.)
Implemented using Click Modular Router (C++)
MIMO-OFDM Ad Hoc Network Prototype
Profs. Robert W. Heath, Jr., Scott Nettles (UT Austin) and Kapil Dandekar (Drexel)
Funding from NSF and NI
Equipment donations from Intel, NI, and TI
Slide by Prof. Robert W. Heath, Jr., UT Austin,

31. Prototyping Ad Hoc Networks: Node Diagram
D A
C C
N N
I I
5 5
6 4
2 2
0 1
MIMO/OFDM
Send
Gigabit
Ethernet
PXI 8231
RF Front-end
(TI)
PHY
Cntrl
MIMO
MAC
Ad-Hoc
Net
App
MIMO/OFDM
Recv
Click Modular
Router (C++)
PXI 8187 Controller
LabVIEW
NI Mb buffer
Dell X86 Linux Host
NI PXI CHASSIS
NI Mb buffer
Slide by Prof. Robert W. Heath, Jr., UT Austin,

32. Prototyping Ad Hoc Networks: Two Nodes
Slide by Prof. Robert W. Heath, Jr., UT Austin,