1. Los tOHMales CalI e ntes Lauren Cash, Chuhong Duan Rebecca Reed, Andrew Tyler ECE 4332: Intro to VLSI

2. Introduction ECE 4332: Intro to VLSI

3. Project: Design a high-speed 64KB SRAM cache Make optimizations that influence power consumption, area and total delay Metric: Delay^2*access-energy*idle-power*area ECE 4332: Intro to VLSI

4. Overview ECE 4332: Intro to VLSI

6. Figure : Simple SRAM 6T Bit Cell (U.Va ECE wiki) Components ECE 4332: Intro to VLSI Sized standard 6T Bit Cell Row decoder: predecode stage (4-16) Column deMUX: precode stage (3-8, 2-4) PreCharge/BL/BLB High Speed Sense Amp Column MUX for output data Figure : Hierarchical decoders

7. The Simulations ECE 4332: Intro to VLSI

8. Simulations

9. ECE 4332: Intro to VLSI Process Corners - FF

10. ECE 4332: Intro to VLSI Process Corners - FS

11. ECE 4332: Intro to VLSI Process Corners - SF

12. ECE 4332: Intro to VLSI Process Corners - SS

13. Layout ECE 4332: Intro to VLSI

14. Single Bit cell Figure : Los tOHMales Calientes, Bit Cell Layout ECE 4332: Intro to VLSI

15. High Speed Sense Amp Figure : Los tOHMales Calientes, Bit Cell Layout ECE 4332: Intro to VLSI

16. Figure : Los tOHMales Calientes, Pre-charge Layout Pre-charge Layout ECE 4332: Intro to VLSI

17. Figure : Los tOHMales Calientes, 32x1 Mux 32x1 Mux ECE 4332: Intro to VLSI

18. Figure : Los tOHMales Calientes, Pre-Decoder Layout Pre-Decoder ECE 4332: Intro to VLSI

19. Figure : Los tOHMales Calientes, Row Decoder Row Decoder ECE 4332: Intro to VLSI

20. Figure : Los tOHMales Calientes, Full Layout Full Layout ECE 4332: Intro to VLSI

21. Optimizations ECE 4332: Intro to VLSI

22. High speed Sense Amp architecture BL/BLB/PRECH Logic Pre-decoder logic Decoder location Square cache architecture Write drive size ECE 4332: Intro to VLSI

23. High Speed Sense Amp Speeded up ~50% Figure. High Speed Sense Amp for Cache Application (Hsu, Ho, (2004)) ECE 4332: Intro to VLSI

24. Write Driver Size Figure. Write delay vs. BL driver size

25. Metrics ECE 4332: Intro to VLSI

26. Power BreakdownValue Bitline charger write power58.34 μW Column decoder write power1.705 μW Row decoder writer power41.28 μW Sense amp write power78.45 μW Bit cell write power:20.03 μW Bitline charger read power16.96 μW Cloumn decoder read power1.05 μW Row decoder read power40.01 μW Sense amp read power137.4 μW Bit cell read power29.89 μW Total write power121.7 μW Total read power237.2 μW ECE 4332: Intro to VLSI

27. MeasurementValue Metric7.34x10 -35 J·s 2 ·mm 2 ·W Single Bitcell Area1.1 μm 2 Total Area0.1148 mm 2 Read Energy0.3558 pJ Write Energy0.18255 pJ Total Energy0.326925 pJ Read Delay.450 ns Write Delay.397 ns Total Delay.770 ns (slower due to recharge) Idle Power3.3 mW ECE 4332: Intro to VLSI

28. References ECE 4332: Intro to VLSI Hsu, C.-L., & Ho, M.-H. (2004). High-speed sense amplifier for SRAM applications. The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings (Vol. 1, pp. 577 – 580 vol.1). Presented at the The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. doi:10.1109/APCCAS.2004.1412828