1. IDE Controller Feasibility Review Group Members b Brian Kulig b Graig Plumb b James Pierpont b Saif Shaikh Advisor b Arun Ramanathan

2. Development of an Ultra DMA Module for a Hard Disk Controller b Specifications – IDE ATA5 Standards b RTL Description of PIO and Ultra DMA (Direct Memory Access) Module in Verilog HDL (Support for PIO Modes 0 to 4 & UltraDMA Modes 0 to 4) b Behavioral description of the Hard Disk Interface b Functional and Timing Simulations using Cadence VerilogXL

3. Architecture IDE FSM IDE FSM DMA MODULE PIO MODULE DMA MODULE PIO MODULE To Hard Disk IDE CHANNEL 0 IDE CHANNEL 1 Fifo’s and Rest of System Fifo’s and Rest of System

4. PIO Mode

5. Programmed I/O Constraints

6. PIO Design b 5 Modes 0 - 4, used for control signals b Timer, begins on start pulse Signals dependent on rwSignals dependent on rw b Timer reset at specific time Example mode 0 resets at 67Example mode 0 resets at 67 b IORDY can delay system up to 1250 ns b Databus enabled by data write

7. Test Bench b It simulates controller for our module b It produces are varying waveforms for the different modes b Evolve into a hard disk with the implementation of UDMA

8. PIO Timing Simulation

9. Finite State Machine

10. Ultra DMA

11. Ultra DMA Constraints

12. Phases of Ultra DMA Data Transfer b Initiating UDMA Data-In (Out) Burst b Data-In (Out) Transfer b Pausing Data-In (Out) Burst b Terminating Data-In (Out) Burst

13. Initiating an Ultra DMA Data-In Burst

14. Sustaining Ultra DMA Data-in Burst

15. Host Termination of Ultra DMA Data-In Burst

16. Device Termination of Ultra DMA Data-in Burst

17. Description of the Host b The Host Has: A Read Buffer and a Write BufferA Read Buffer and a Write Buffer Ability to cycle through and request all modes of data transferAbility to cycle through and request all modes of data transfer Ability to Calculate CRC Values as well as periodically send an error to the controllerAbility to Calculate CRC Values as well as periodically send an error to the controller

18. CRC Error Checking Design b Process: Both Devices are initialized with 4ABABoth Devices are initialized with 4ABA Value is modified on every STROBE pulseValue is modified on every STROBE pulse –using G(X) = X16 + X12 + X5 + 1 Host ---> CRC ---> ControllerHost ---> CRC ---> Controller Bits 2 & 7 in Error Register go highBits 2 & 7 in Error Register go high <----- 04 HARDWARE ERROR<----- 04 HARDWARE ERROR Host Should Retry last commandHost Should Retry last command

19. Gantt Chart

20. Who’s doing What. b Saif: Program DMA mode RTL Code, Update Website b James: Program DMA mode RTL b Brian: Implement Error Checking, Describe Host in Behavioral Verilog b Graig: Interface PIO Mode with DMA, Describe Hardrive in Behavioral Verilog

21. Finishing Everything on Time b Our Goal is finishing on May 8th b We have all the tools and know how to use them. b We have all the specifications in hand. b All team members know their tasks

22. References b General IDE Information: pcguide.compcguide.com hardwarecentral.comhardwarecentral.com b ATA5 Specification: t13.org b Our Website: www-unix.ecs.umass.edu/~sashaikh/ece559/index.htmlwww-unix.ecs.umass.edu/~sashaikh/ece559/index.html