1. ELEN468 Lecture 101 ELEN 468 Advanced Logic Design Lecture 10 Behavioral Descriptions IV

2. ELEN468 Lecture 102 Finite State Machines Next state and output Combinational logic Next state and output Combinational logic Register clock inputoutput Next state Combinational logic Next state Combinational logic Register Output Combinational logic Output Combinational logic input output clock Mealy Machine Moore Machine

3. ELEN468 Lecture 103 Explicit Finite State Machines 1 module FSM_style1 ( … ); input …; output …; parameter size = …; reg [size-1:0] state; wire [size-1:0] next_state; // different from textbook // which is wrong assign outputs = …; // function of state and inputs assign next_state = …; // function of state and inputs always @ ( negedge reset or posedge clk ) if ( reset == 1`b0 ) state = start_state; else state <= next_state; endmodule module FSM_style1 ( … ); input …; output …; parameter size = …; reg [size-1:0] state; wire [size-1:0] next_state; // different from textbook // which is wrong assign outputs = …; // function of state and inputs assign next_state = …; // function of state and inputs always @ ( negedge reset or posedge clk ) if ( reset == 1`b0 ) state = start_state; else state <= next_state; endmodule

4. ELEN468 Lecture 104 Explicit Finite State Machines 2 module FSM_style2 ( … ); input …; output …; parameter size = …; reg [size-1:0] state, next_state; assign outputs = …; // function of state and inputs always @ ( state or inputs ) begin // decode for next_state with case or if statement end always @ ( negedge reset or posedge clk ) if ( reset == 1`b0 ) state = start_state; else state <= next_state; endmodule module FSM_style2 ( … ); input …; output …; parameter size = …; reg [size-1:0] state, next_state; assign outputs = …; // function of state and inputs always @ ( state or inputs ) begin // decode for next_state with case or if statement end always @ ( negedge reset or posedge clk ) if ( reset == 1`b0 ) state = start_state; else state <= next_state; endmodule

5. ELEN468 Lecture 105 Explicit Finite State Machines 3 module FSM_style3 ( … ); input …; output …; parameter size = …; reg [size-1:0] state, next_state; always @ ( state or inputs ) begin // decode for next_state with case or if statement end always @ ( negedge reset or posedge clk ) if ( reset == 1`b0 ) state = start_state; else begin state <= next_state; outputs <= some_value ( inputs, next_state ); end endmodule module FSM_style3 ( … ); input …; output …; parameter size = …; reg [size-1:0] state, next_state; always @ ( state or inputs ) begin // decode for next_state with case or if statement end always @ ( negedge reset or posedge clk ) if ( reset == 1`b0 ) state = start_state; else begin state <= next_state; outputs <= some_value ( inputs, next_state ); end endmodule

6. ELEN468 Lecture 106 Summary of Explicit FSM States are defined explicitly FSM_style1 Minimum behavioral description FSM_style2 Use behavioral to define next state, easier to use FSM_style3 Output synchronized with clock

7. ELEN468 Lecture 107 FSM Example: Speed Machine speed accelerator brake clock medium lowstopped high a: accelerator b: brake a = 1, b = 0 b = 1 a = 1, b = 0

8. ELEN468 Lecture 108 Verilog Code for Speed Machine // Explicit FSM style module speed_machine ( clock, accelerator, brake, speed ); inputclock, accelerator, brake; output [1:0]speed; reg [1:0]state, next_state; parameter stopped = 2`b00; parameter s_slow = 2`b01; parameter s_medium = 2`b10; parameter s_high = 2`b11; assign speed = state; always @ ( posedge clock ) state <= next_state; // Explicit FSM style module speed_machine ( clock, accelerator, brake, speed ); inputclock, accelerator, brake; output [1:0]speed; reg [1:0]state, next_state; parameter stopped = 2`b00; parameter s_slow = 2`b01; parameter s_medium = 2`b10; parameter s_high = 2`b11; assign speed = state; always @ ( posedge clock ) state <= next_state; always @ ( state or accelerator or brake ) if ( brake == 1`b1 ) case ( state ) stopped: next_state <= stopped; s_low: next_state <= stopped; s_medium: next_state <= s_low; s_high: next_state <= s_medium; default: next_state <= stopped; endcase else if ( accelerator == 1`b1 ) case ( state ) stopped: next_state <= s_low; s_low: next_state <= s_medium; s_medium: next_state <= s_high; s_high: next_state <= s_high; default: next_state <= stopped; endcase else next_state <= state; endmodule always @ ( state or accelerator or brake ) if ( brake == 1`b1 ) case ( state ) stopped: next_state <= stopped; s_low: next_state <= stopped; s_medium: next_state <= s_low; s_high: next_state <= s_medium; default: next_state <= stopped; endcase else if ( accelerator == 1`b1 ) case ( state ) stopped: next_state <= s_low; s_low: next_state <= s_medium; s_medium: next_state <= s_high; s_high: next_state <= s_high; default: next_state <= stopped; endcase else next_state <= state; endmodule

9. ELEN468 Lecture 109 Implicit Finite State Machine module speed_machine2 ( clock, accelerator, brake, speed ); input clock, accelerator, brake; output [1:0] speed; reg [1:0] speed; `define stopped 2`b00 `define low 2`b01 `define medium 2`b10 `define high 2`b11 module speed_machine2 ( clock, accelerator, brake, speed ); input clock, accelerator, brake; output [1:0] speed; reg [1:0] speed; `define stopped 2`b00 `define low 2`b01 `define medium 2`b10 `define high 2`b11 always @ ( posedge clock ) if ( brake == 1`b1 ) case ( speed ) `stopped: speed <= `stopped; `low: speed <= `stopped; `medium: speed <= `low; `high: speed <= `medium; default: speed <= `stopped; endcase else if ( accelerator == 1`b1 ) case ( speed ) `stopped: speed <= `low; `low: speed <= `medium; `medium: speed <= `high; `high: speed <= `high; default: speed <= `stopped; endcase endmodule always @ ( posedge clock ) if ( brake == 1`b1 ) case ( speed ) `stopped: speed <= `stopped; `low: speed <= `stopped; `medium: speed <= `low; `high: speed <= `medium; default: speed <= `stopped; endcase else if ( accelerator == 1`b1 ) case ( speed ) `stopped: speed <= `low; `low: speed <= `medium; `medium: speed <= `high; `high: speed <= `high; default: speed <= `stopped; endcase endmodule

10. ELEN468 Lecture 1010 Another Implicit FSM Example module speed_machine3 ( clock, accelerator, brake, speed ); input clock, accelerator, brake; output [1:0] speed; reg [1:0] speed; `define stopped 2`b00 `define low 2`b01 `define medium 2`b10 `define high 2`b11 module speed_machine3 ( clock, accelerator, brake, speed ); input clock, accelerator, brake; output [1:0] speed; reg [1:0] speed; `define stopped 2`b00 `define low 2`b01 `define medium 2`b10 `define high 2`b11 always @ ( posedge clock ) case ( speed ) `stopped: if ( brake == 1`b1 ) speed <= `stopped; else if ( accelerator == 1`b1 ) speed <= `low; `low: if ( brake == 1`b1 ) speed <= `stopped; else if ( accelerator == 1`b1 ) speed <= `medium; `medium: if ( brake == 1`b1 ) speed <= `low; else if ( accelerator == 1`b1 ) speed <= `high; `high: if ( brake == 1`b1 ) speed <= `medium; default: speed <= `stopped; endcase endmodule always @ ( posedge clock ) case ( speed ) `stopped: if ( brake == 1`b1 ) speed <= `stopped; else if ( accelerator == 1`b1 ) speed <= `low; `low: if ( brake == 1`b1 ) speed <= `stopped; else if ( accelerator == 1`b1 ) speed <= `medium; `medium: if ( brake == 1`b1 ) speed <= `low; else if ( accelerator == 1`b1 ) speed <= `high; `high: if ( brake == 1`b1 ) speed <= `medium; default: speed <= `stopped; endcase endmodule

11. ELEN468 Lecture 1011 Handshaking ServerClient 8 data_out server_ready client_ready data_in server_ready client_ready

12. ELEN468 Lecture 1012 Algorithm State Machine (ASM) Chart s_idle / SR = 0 s_wait / SR = 1 s_serve / SR = 1c_client / CR = 1 c_done / CR = 0 c_wait / CR = 1 c_idle / CR = 0 CR SR 00 0 0 1 11 # # # # s_done / SR = 0 # # # 1 #

13. ELEN468 Lecture 1013 Verilog Code for Handshaking module server ( d_out, s_ready, c_ready ); output [3:0] d_out; output s_ready; input c_ready; reg s_ready; reg [3:0] d_out; task pause; reg [3:0] delay; begin delay = $random; if ( delay == 0 ) delay = 1; #delay; end endtask always forever begin s_ready = 0; pause; s_ready = 1; wait ( c_ready ) pause; d_out = $random; pause; s_ready = 0; wait ( !c_ready ) pause; end endmodule module server ( d_out, s_ready, c_ready ); output [3:0] d_out; output s_ready; input c_ready; reg s_ready; reg [3:0] d_out; task pause; reg [3:0] delay; begin delay = $random; if ( delay == 0 ) delay = 1; #delay; end endtask always forever begin s_ready = 0; pause; s_ready = 1; wait ( c_ready ) pause; d_out = $random; pause; s_ready = 0; wait ( !c_ready ) pause; end endmodule module client ( d_in, s_ready, c_ready ); input [3:0] d_in; input s_ready; output c_ready; reg c_ready; reg [3:0] data_reg; task pause; reg [3:0] delay; begin delay = $random; if ( delay == 0 ) delay = 1; #delay; end endtask always begin c_ready = 0; pause; c_ready = 1; forever begin wait ( s_ready ) pause; data_reg = d_in; pause; c_ready = 0; wait ( !s_ready ) pause; c_ready = 1; end endmodule module client ( d_in, s_ready, c_ready ); input [3:0] d_in; input s_ready; output c_ready; reg c_ready; reg [3:0] data_reg; task pause; reg [3:0] delay; begin delay = $random; if ( delay == 0 ) delay = 1; #delay; end endtask always begin c_ready = 0; pause; c_ready = 1; forever begin wait ( s_ready ) pause; data_reg = d_in; pause; c_ready = 0; wait ( !s_ready ) pause; c_ready = 1; end endmodule

14. ELEN468 Lecture 1014 Polling Circuit client1 client2 client3 Server Polling circuit 3 2 clock reset service request service code Highest priority Each client cannot be served for 2 consecutive cycles

15. ELEN468 Lecture 1015 State Transition Graph for Polling Circuit None 00 Client3 11 Client2 10 Client1 01 100 1-- 001 000 001 000 0-1 01- 010 -1- 1-- 000 Service code Service request

16. ELEN468 Lecture 1016 Verilog Code for Polling Circuit module polling ( s_request, s_code, clk, rst ); `define client1 2`b01 `define client2 2`b10 `define client3 2`b11 `define none 2`b00 input [3:1] s_request; input clk, rst; output [1:0] s_code; reg [1:0] next_client, present_client; always @ ( posedge clk or posedge rst ) begin if ( rst ) present_client = `none; else present_client = next_client; end assign s_code[1:0] = present_client; always @ ( present_client or s_request ) begin poll_them ( present_client, s_request, next_client ); end module polling ( s_request, s_code, clk, rst ); `define client1 2`b01 `define client2 2`b10 `define client3 2`b11 `define none 2`b00 input [3:1] s_request; input clk, rst; output [1:0] s_code; reg [1:0] next_client, present_client; always @ ( posedge clk or posedge rst ) begin if ( rst ) present_client = `none; else present_client = next_client; end assign s_code[1:0] = present_client; always @ ( present_client or s_request ) begin poll_them ( present_client, s_request, next_client ); end task poll_them; input [1:0] present_client; input [3:1] s_request; output [1:0] next_client; reg [1:0] contender; integer N; begin: poll contender = `none; next_client = `none; for ( N = 3; N >= 1; N = N – 1 ) begin: decision if ( s_request[N] ) begin if ( present_client == N ) contender = present_client; else begin next_client = N; disable poll; end end end if (( next_client == `none ) && ( contender )) next_client = contender; end endtask endmodule task poll_them; input [1:0] present_client; input [3:1] s_request; output [1:0] next_client; reg [1:0] contender; integer N; begin: poll contender = `none; next_client = `none; for ( N = 3; N >= 1; N = N – 1 ) begin: decision if ( s_request[N] ) begin if ( present_client == N ) contender = present_client; else begin next_client = N; disable poll; end end end if (( next_client == `none ) && ( contender )) next_client = contender; end endtask endmodule

17. ELEN468 Lecture 1017 Test Bench for Polling Circuit moduel test_polling; reg [3:1] s_request; reg clk, rst; wire [1:0] s_code; wire sreq3 = M1.s_request[3]; wire sreq2 = M1.s_request[2]; wire sreq1 = M1.s_request[1]; wire [1:0] NC = M1.next_client; wire [1:0] PC = M1.present_client; wire [3:1] s_req = s_request; wire [1:0] s_cd = s_code; polling M1 ( s_request, s_code, clk, rst ); initial begin clk = 0; forever #10 clk = ~clk; end initial #400 finish; initial begin rst = 1`bx; #25 rst = 1; #75 rst = 0; end moduel test_polling; reg [3:1] s_request; reg clk, rst; wire [1:0] s_code; wire sreq3 = M1.s_request[3]; wire sreq2 = M1.s_request[2]; wire sreq1 = M1.s_request[1]; wire [1:0] NC = M1.next_client; wire [1:0] PC = M1.present_client; wire [3:1] s_req = s_request; wire [1:0] s_cd = s_code; polling M1 ( s_request, s_code, clk, rst ); initial begin clk = 0; forever #10 clk = ~clk; end initial #400 finish; initial begin rst = 1`bx; #25 rst = 1; #75 rst = 0; end initial begin #20 s_request = 3`b100; #20 s_request = 3`b010; #20 s_request = 3`b001; #20 s_request = 3`b100; #40 s_request = 3`b010; #40 s_request = 3`b001; end initial begin #180 s_request = 3`b111; #60 s_request = 3`b101; #60 s_request = 3`b011; #60 s_request = 3`b111; #20 rst = 1; end endmodule initial begin #20 s_request = 3`b100; #20 s_request = 3`b010; #20 s_request = 3`b001; #20 s_request = 3`b100; #40 s_request = 3`b010; #40 s_request = 3`b001; end initial begin #180 s_request = 3`b111; #60 s_request = 3`b101; #60 s_request = 3`b011; #60 s_request = 3`b111; #20 rst = 1; end endmodule

18. ELEN468 Lecture 1018 Exercise 2

19. ELEN468 Lecture 1019 Find Error module something_wrong ( y_out, x1, x2 ); output y_out; input x1, x2; `define delay1 3; // No “;” `define delay2 4; `define delay3 5; nand #(delay1, delay2, delay3) ( y_out, x1, x2 ); // No turnoff delay for non-3-state gate // Remove “delay3”, or replace “,” with “:” endmodule module something_wrong ( y_out, x1, x2 ); output y_out; input x1, x2; `define delay1 3; // No “;” `define delay2 4; `define delay3 5; nand #(delay1, delay2, delay3) ( y_out, x1, x2 ); // No turnoff delay for non-3-state gate // Remove “delay3”, or replace “,” with “:” endmodule

20. ELEN468 Lecture 1020 Timing Models Determine time values in simulation `timescale 10ns/1ps 2.447 24.470ns `timescale 1ns/100ps 2.447 2.4ns What is the typical falling delay from a1 to y2? (a1,a2 *> y1, y2) = (7:8:9, 6:10:12); 10

21. ELEN468 Lecture 1021 Correct Error module flop ( clock, data, q, qbar, reset ); input clock, data, reset; output q, qbar; reg q; assign qbar = ~q; // This cannot model flip-flop properly // when reset rises and clock == 1 always @ ( posedge clock or reset ) begin if ( reset == 0 ) q = 0; else if ( clock == 1 ) q = data; end endmodule module flop ( clock, data, q, qbar, reset ); input clock, data, reset; output q, qbar; reg q; assign qbar = ~q; // This cannot model flip-flop properly // when reset rises and clock == 1 always @ ( posedge clock or reset ) begin if ( reset == 0 ) q = 0; else if ( clock == 1 ) q = data; end endmodule

22. ELEN468 Lecture 1022 What will happen? module A ( … ); … initial clock = 0; // Nothing will happen always @ ( clock ) clock = ~clock; … endmodule module A ( … ); … initial clock = 0; // Nothing will happen always @ ( clock ) clock = ~clock; … endmodule