1. Network for Computational Nanotechnology (NCN) UC Berkeley, Univ.of Illinois, Norfolk State, Northwestern, Purdue, UTEP First Time User Guide to PN Junction V1.31 Saumitra R Mehrotra*, Ben Haley & Gerhard Klimeck Network for Computational Nanotechnology (NCN) Electrical and Computer Engineering http://nanohub.org/resources/229 *smehrotr@purdue.edu

2. Saumitra R Mehrotra Outline  Introduction  What is a PN Junction?  Working of a PN Junction.  What can be simulated by in PN Junction Lab?  What if you just hit “Simulate”?  Examples  What if the doping is changed?  What if the intrinsic region is included (e.g. PIN diode)?  Limitation/Comments  References

3. Saumitra R Mehrotra What is a PN Junction? A PN junction is a device formed by combining p-type ( doped with B,Al) and n-type (doped with P,As,Sb) semiconductors together in close contact. PN junction can basically work in two modes, »forward bias mode (as shown below: positive terminal connected to p- region and negative terminal connected to n region) »reverse bias mode ( negative terminal connected to p-region and positive terminal connected to n region) PN junction device

4. Saumitra R Mehrotra Working of a PN junction Refer https://nanohub.org/resources/68 for a detailed discussion on operation of PN junction.https://nanohub.org/resources/68 Forward Bias Reverse Bias Zener or Avalanche Breakdown Voltage Current I-V characteristic of a PN junction diode. PN junction diode acts as a rectifier as seen in the IV characteristic. Certain current flows in forward bias mode. Negligible current flows in reverse bias mode until zener or avalanche breakdown happens.

5. Saumitra R Mehrotra What can be simulated in PN junction lab? PN junction device structure Specify P-type region length. (More number of nodes lead to higher resolution but also more compute time) Specify N-type region length Specify intrinsic region length Specify doping level for P- type and N-type region.

6. Saumitra R Mehrotra What can be simulated in PN junction lab? PN junction material definition Specify the material to be simulated (Si,Ge,GaAs) Specify intrinsic minority carrier lifetime (s).

7. Saumitra R Mehrotra What can be simulated in PN junction lab? PN junction environment definition Specify temperature (K). Specify applied voltage and number of steps.

8. Saumitra R Mehrotra What can be simulated in PN junction lab? PN junction output plots Default settings will simulate : PN junction diode in forward bias mode with, 1  m long P-type and N-type regions doped at 1e17 cm 3. 

9. Saumitra R Mehrotra What if you just hit simulate? IV characteristic for PN junction in forward bias mode in default settings. Knee voltage Current increases slightly till Knee Voltage*. Beyond it current rises exponentially. *Refer https://nanohub.org/resources/68 for a detailed discussion on operation of PN junction.https://nanohub.org/resources/68

10. Saumitra R Mehrotra What if you just hit simulate? C  d –1 [1]&[2] where, C : capacitance across PN junction & d : depletion width* (insulating region at the junction where carriers have diffused away or have been swept by the electric field.) Increasing bias  decreasing depletion width  Increasing Capacitance C-V characteristic for PN junction in forward bias mode in default settings. *Refer https://nanohub.org/resources/68 for a detailed discussion on operation of PN junction.https://nanohub.org/resources/68

11. Saumitra R Mehrotra What if you just hit simulate? Built in charge, electric field and potential at equilibrium. Built in charge Built in electric field N-regionP-region N-region Built in potential, V bi = 0.834V

12. Saumitra R Mehrotra What if you just hit simulate? Built in charge, electric field and potential at forward bias V a =0.6V Decreasing charge with applied bias due to thinning of depletion width. P-regionN-region P-region Decreasing electric field with applied bias due to thinning of depletion width. Potential difference V bi -V a = 0.234V Positive bias at P side reduces the barrier leading to increase in diode current. Increased diffusion of electrons across the barrier lowered by V a.

13. Saumitra R Mehrotra What if doping is changed? Doping= 1e16 cm 3 Doping= 1e18 cm 3 Increasing doping leads to increasing built in potential, V bi [1],[2]. N a : P region doping level (cm -3 ). N d : N region doping level (cm -3 ). n i : Intrinsic carrier density (cm -3 ). K b T : Thermal voltage (= 0.0259 V). = V bi On changing doping for both n-type and p-type regions from 1e16 cm 3 to 1e18 cm 3.

14. Saumitra R Mehrotra What if intrinsic region is included i.e PIN diode? On introducing an intrinsic region of length 0.2  m with default setting. Increased depletion width (d) due to addition of intrinsic region as seen in energy band diagram. Junction Capacitance, C j  d -1 shows a decrease as seen in CV characteristic. PIN diode (bold) PN diode (light)

15. Saumitra R Mehrotra Limitations/Comments Large physical dimensions (>10um) might lead to non convergence or large compute time. More nodes might be required for better convergence in some cases i.e. high doping in PN junction. PN junction currently performs steady state simulations only, no time dependent simulations are possible. Contacts during the simulation are considered to be ohmic (i.e. Current-Voltage,I-V curve is linear and symmetric).

16. Saumitra R Mehrotra References PN junction theory [1] PN junction OPERATION : https://nanohub.org/resources/68https://nanohub.org/resources/68 [2] “Semiconductor Device Fundamentals”, by R.F. Pierret PADRE [3] Dragica Vasileska; Gerhard Klimeck (2006), "Padre," DOI: 10254/ nanohub-r941.3.DOI [4] PADRE MANUAL : http://nanohub.org/resource_files/tools/padre/doc/ index.htmlhttp://nanohub.org/resource_files/tools/padre/doc/ index.html Please report any comment/review at the following link, https://nanohub.org/resources/pntoy/reviews If you reference this work in a publication, please cite as follows: Matteo Mannino; Dragica Vasileska; Michael McLennan; Xufeng Wang; Gerhard Klimeck (2005), "PN Junction Lab," DOI: 10254/nanohub-r229.9.