1. The Belle II Silicon Vertex Detector Readout Chain Markus Friedl (HEPHY Vienna) TWEPP2012, 19 September 2012

2. 19 September 2012M.Friedl (HEPHY Vienna): Belle II SVD Readout2 Introduction Front-End Junction Box FADC DAQ Summary

3. 19 September 2012M.Friedl (HEPHY Vienna): Belle II SVD Readout3 Introduction Front-End Junction Box FADC DAQ Summary

4. KEKB and Belle @ KEK (1999-2010)  Center of mass energy: Y(4S) (10.58 GeV)  High intensity beams (1.6 A & 1.3 A)  Integrated luminosity of 1 ab -1 recorded in total  Belle mentioned explicitly in 2008 Physics Nobel Prize announcement to Kobayashi and Masukawa Linac Belle KEKB ~1 km in diameter KEKB Belle Linac About 60km northeast of Tokyo  Asymmetric machine: 8 GeV e - on 3.5 GeV e + 19 September 2012M.Friedl (HEPHY Vienna): Belle II SVD Readout4

5. µ / K L detection 14/15 lyr. RPC+Fe CsI(Tl) 16 X 0 Si vertex detector 4 layers DSSD SC solenoid 1.5 T 8 GeV e - 3.5 GeV e + Aerogel Cherenkov counter n=1.015~1.030 Central Drift Chamber small cell +He/C 2 H 5 TOF counter Belle Detector (1999–2010) 19 September 2012M.Friedl (HEPHY Vienna): Belle II SVD Readout5

6. SuperKEKB/Belle II Upgrade: 2010–2015  Aim: super-high luminosity ~8  10 35 cm -2 s -1  1  10 10 BB / year  LoI published in 2004; TDR published in 2010  Refurbishment of accelerator and detector required  nano-beams with cross-sections of ~10 µm x 60 nm  10 mm radius beam pipe at interaction region 19 September 2012M.Friedl (HEPHY Vienna): Belle II SVD Readout6 http://belle2.kek.jp

7. Previous SVD Layout (until 2010)  4 straight layers of 4" double-sided silicon detectors (DSSDs)  Outer radius of r~8.8 cm  Up to three 4” sensors are daisy-chained and read out by one hybrid located outside of acceptance region (VA1 chip) 19 September 2012M.Friedl (HEPHY Vienna): Belle II SVD Readout7

8. Belle Silicon Vertex Detector (SVD) Current SVD is not suitable for Belle II 19 September 2012M.Friedl (HEPHY Vienna): Belle II SVD Readout8 10%  Previous SVD limitations were  occupancy (~10% in innermost layer)  need faster shaping  dead time (~3%)  need faster readout and pipeline  Belle II needs detector with  high background tolerance  pipelined readout  robust tracking  low material budget in active volume

9. New Layout for Belle II SVD (2015-)  New double-layer pixel detector using DEPFET technology  Four layers with 6” double-sided strip detectors and forward part  Optimized for precision vertex reconstruction of the decays of short-lived B-mesons Two layers of DEPFET pixels 4 layers of double- sided strip sensors 19 September 2012M.Friedl (HEPHY Vienna): Belle II SVD Readout9

10. 19 September 2012M.Friedl (HEPHY Vienna): Belle II SVD Readout10 APV25 chips Cooling pipe Origami ladder Sensor underneath flex circuit Pitch adapter bent around sensor edge End ring (support)

11. Readout Chain Overview  Analog APV25 readout is through copper cable to FADCs  Junction box provides LV to front-end 19 September 2012M.Friedl (HEPHY Vienna): Belle II SVD Readout11 1748 APV25 chips Front-end hybrids Rad-hard DC/DC converters Analog level translation, data sparsification and hit time reconstruction Unified Belle II DAQ system ~2m copper cable Junction box ~10m copper cable FADC Unified optical data link (>20m) Finesse Transmitter Board (FTB) COPPER

12. Not Entirely New…  2007: plans for an intermediate upgrade of Belle I SVD  Prototype system built and tested thoroughly in several beam tests since then  Now enlarging and improving details, but concept is same  See reports at previous TWEPPs for details & performance 19 September 2012M.Friedl (HEPHY Vienna): Belle II SVD Readout12

13. 19 September 2012M.Friedl (HEPHY Vienna): Belle II SVD Readout13 Introduction Front-End Junction Box FADC DAQ Summary

14. APV25 Readout Chip  Developed for CMS (LHC) by IC London and RAL (70k chips installed)  0.25 µm CMOS process (>100 MRad tolerant)  40 MHz clock (adjustable), 128 channels  192 cell analog pipeline  no dead time  50 ns shaping time  low occupancy  Noise: 250 e + 36 e/pF  must minimize capacitive load!!!  Multi-peak mode (read out several samples along shaping curve)  Thinning to 100µm successful Schematics of one channel 19 September 2012M.Friedl (HEPHY Vienna): Belle II SVD Readout14

15. Front-End Hybrids  2 variants  Standard PCBs outside acceptance for the edge sensors  “Origami” chip-on-sensor concept for inner sensors 19 September 2012M.Friedl (HEPHY Vienna): Belle II SVD Readout15 See presentation by C. Irmler today at 14:50 Martin Wood Lecture Theater

16. 19 September 2012M.Friedl (HEPHY Vienna): Belle II SVD Readout16 Introduction Front-End Junction Box FADC DAQ Summary

17. Junction Box: Mother Board  Junction box board with CERN DC/DC converters to be placed in SVD DOCK boxes  Converter boards now have a commercial chip, to be replaced by the rad-hard AMIS5 chip 19 September 2012M.Friedl (HEPHY Vienna): Belle II SVD Readout17

18. DC/DC Converter: Noise Comparison  Same noise within measurement precision (few %) between conventional and DC/DC powering! 19 September 2012M.Friedl (HEPHY Vienna): Belle II SVD Readout18 Test hybrid (larger) Belle II design (smaller)

19. Junction Box: Draft Design  (Top lid not shown)  As in Belle 1 SVD: Located ~2m from front-end (outside acceptance) = radiation zone  Mostly aluminum, only bottom plate copper (to be cooled) 19 September 2012M.Friedl (HEPHY Vienna): Belle II SVD Readout19

20. 19 September 2012M.Friedl (HEPHY Vienna): Belle II SVD Readout20 Introduction Front-End Junction Box FADC DAQ Summary

21. Readout Electronics: Scheme 19 September 2012M.Friedl (HEPHY Vienna): Belle II SVD Readout21  No direct connection between power supplies and FADC  Bias currents are measured remotely by FADC

22. FADC Block Diagram  Analog & digital level translation between  bias and GND  Digitization, signal conditioning (FIR filter), data processing  Central FPGA is an Altera Stratix IV GX 19 September 2012M.Friedl (HEPHY Vienna): Belle II SVD Readout22

23. FADC: Overall Concept  Similar to Belle 1 SVD FADC, but with twice higher density (48 APV25 inputs) and more powerful FPGA 19 September 2012M.Friedl (HEPHY Vienna): Belle II SVD Readout23

24. FADC: Level Translation Daughter Boards  Analog board: existing design, but simplified  Digital board: completely new design based on digital isolator ICs (Analog Devices)  No floating LV power needed for either board! 19 September 2012M.Friedl (HEPHY Vienna): Belle II SVD Readout24

25. FADC: Level Translation Tests 19 September 2012M.Friedl (HEPHY Vienna): Belle II SVD Readout25  Both boards tested thoroughly, working perfectly fine  Short (2m) and long (12m) cable to FADC   100V between floating and GND sides  No damage with repeated instantaneous shorting of HV APVDAQ Repeater Ana+Digi daughter boards on adapter board APV25 Hybrid

26. 19 September 2012M.Friedl (HEPHY Vienna): Belle II SVD Readout26 Introduction Front-End Junction Box FADC DAQ Summary

27. Finesse Transmitter Board (FTB)  Sends FADC data through optical link to  COPPER  Pixel system (for online data reduction)  Firmware in development 12 November 2011Markus Friedl (HEPHY Vienna): Status of SVD27

28. COPPER = Common Readout Platform  Standardized 9U VME crate with CPU and network interface  4 slots for FINESSE daughter boards (ADC, TDC, …) according to subsystem needs  In case of SVD: Belle2Link (Optical receiver) 19 September 2012M.Friedl (HEPHY Vienna): Belle II SVD Readout28

29. 19 September 2012M.Friedl (HEPHY Vienna): Belle II SVD Readout29 Introduction Front-End Junction Box FADC DAQ Summary

30. Overall Readout System Scheme  DAQ: PC Farm  COPPER: common readout platform  FADC system with optical link to COPPER  DOCK box with DC/DC  Front-End 19 September 2012M.Friedl (HEPHY Vienna): Belle II SVD Readout30

31. Summary & Outlook  Belle I  Belle II  Needs completely new vertex detector (pixel + strips)  Readout Chain  Based on a 2007 design (for an earlier update option)  “Origami” chip-on-sensor concept for front-end with APV25  Junction box near front-end with rad-hard DC/DC converters  No noise penalty from switching power  FADC with powerful FPGA for online signal processing  Level translation daughter boards – working fine  DAQ link to common readout platform  Will report on performance at next TWEPP 19 September 2012M.Friedl (HEPHY Vienna): Belle II SVD Readout31