1. ELEN 468 Lecture 41 ELEN 468 Advanced Logic Design Lecture 4 Data Types and Operators

2. ELEN 468 Lecture 42 Variables Represent values of signals in physical circuit in a digital format Nets – Represent physical connectivity Registers – Abstractions of storage elements Nets and registers may be either scalars or vectors

3. ELEN 468 Lecture 43 Storage Variable Storage variable = register reg, integer, real, realtime, time Abstraction of storage element Need not correspond directly to physical storage element in circuit Static – its value is assigned under program flow

4. ELEN 468 Lecture 44 Value Assignment Explicitly – through behavioral statements Implicitly – driven by a gate A net may be assigned value explicitly only through continuous assignment A register variable may be assigned value only within a behavior

5. ELEN 468 Lecture 45 Verilog Nets wire (default) tri wand wor triand trior tri wand/wor triand/trior Not recommended!

6. ELEN 468 Lecture 46 Example tri y; bufif1(y, x, ctrl); triand y; bufif1(y, x1, ctrl1); bufif1(y, x2, ctrl2); ctrl y x ctrl1 ctrl2 x1 x2 y Three-state gate, page 651

7. ELEN 468 Lecture 47 Truth Tables wire/tri01xz 00xx0 1x1x1 xxxxx z01xz triand / wand01xz 00000 101x1 x0xxx z01xz trior/wor 01xz 0 01x0 1 1111 x x1xx z 01xz

8. ELEN 468 Lecture 48 More Verilog Nets supply0 supply1 tri0 tri1 trireg Vdd supply1 supply0 Gnd Vdd tri1 Gnd tri0 a b trireg when a = b = 0, the line maintains its value

9. ELEN 468 Lecture 49 Net Declaration wire[7:0] data_bus;// 8-bit vector wire, data_bus[7] -> MSB wire[0:3] control_bus;// control_bus[0] -> MSB data_bus[5], data_bus[3:5], data_bus[k+2]// access wire scalared[7:0] bus_a;// “scalared” is default wire vectored[7:0] bus_b; // Individual bits may not be referenced wire y1, z_5;// Multiple declaration wire A = B+C, D = E+F;// Implicit continuous assignment wand A, B, C; trireg[7:0] A; wire[7:0] data_bus;// 8-bit vector wire, data_bus[7] -> MSB wire[0:3] control_bus;// control_bus[0] -> MSB data_bus[5], data_bus[3:5], data_bus[k+2]// access wire scalared[7:0] bus_a;// “scalared” is default wire vectored[7:0] bus_b; // Individual bits may not be referenced wire y1, z_5;// Multiple declaration wire A = B+C, D = E+F;// Implicit continuous assignment wand A, B, C; trireg[7:0] A;

10. ELEN 468 Lecture 410 Initial Values At time t sim = 0 Nets driven by primitives, module or continuous assignment is determined by their drivers, default value “x” Net without driver, its initial value “z” Default initial value for register -> “x”

11. ELEN 468 Lecture 411 Register Data Types reg – stores a logic value integer – support computation time – stores time as a 64-bit unsigned quantity real – stores values as real numbers realtime – store time values as real numbers reg – stores a logic value integer – support computation time – stores time as a 64-bit unsigned quantity real – stores values as real numbers realtime – store time values as real numbers Assigned value only within a procedural statement, a user defined sequential primitive, task or function A reg object may never be output of a primitive gate the target of a continuous assignment Undeclared identifier is assumed as a net, which is illegal within behavior

12. ELEN 468 Lecture 412 Addressing Net and Register Variables MSB of a part-select of a register = leftmost array index LSB = rightmost array index If index of part-select is out of bounds, “x” is returned If word [7:0] = 8’b00000100 word [3:0] = 4 word [5:1] = 2 Integer array integer A[3:0];

13. ELEN 468 Lecture 413 Variables and Ports Variable typeInput portOutput portInout port NetYes RegisterNoYesNo An input port is implicitly a net variable

14. ELEN 468 Lecture 414 Memories … reg[31:0] cache_memory[0:1023]; reg[31:0] word_register; reg[7:0] instr_register; … word_register = cache_memory[17]; … // a loop … instr_register[k] = word_register[k+4]; … reg[31:0] cache_memory[0:1023]; reg[31:0] word_register; reg[7:0] instr_register; … word_register = cache_memory[17]; … // a loop … instr_register[k] = word_register[k+4]; … Individual bits within a memory cannot be addressed directly The word is fetched to a register, then bit can be accessed Memory sizeWord size

15. ELEN 468 Lecture 415 Scope of a Variable The scope of a variable is the module, task, function, or named procedural block (begin … end) in which it is declared

16. ELEN 468 Lecture 416 De-Reference To reference a variable defined inside an instantiated module X.w X.Y.Z.w Module A - Instance X Module B - Instance Y Module C - Instance Z wire w

17. ELEN 468 Lecture 417 Example of De-referencing module testbench(); reg [3:0] a, b; wire [3:0] y; adder M1 (y, a, b); initial $monitor($time,,”%”, M1.c); endmodule module adder(y, a, b); … wire c; … endmodule module testbench(); reg [3:0] a, b; wire [3:0] y; adder M1 (y, a, b); initial $monitor($time,,”%”, M1.c); endmodule module adder(y, a, b); … wire c; … endmodule

18. ELEN 468 Lecture 418 Strings Verilog does not have type for strings A string must be stored in a register array reg [8*num_char-1 : 0] string_holder;

19. ELEN 468 Lecture 419 Constants Declared with keyword parameter Value may not be changed during simulation parameter width = 32, depth = 1024; parameter real_value = 6.22; parameter av_delay = (dmin + dmax)/2; parameter width = 32, depth = 1024; parameter real_value = 6.22; parameter av_delay = (dmin + dmax)/2;

20. ELEN 468 Lecture 420 Direct Substitution of Parameters module modXnor(y, a, b); parameter size=8, delay=15; output [size-1:0] y; input [size-1:0] a, b; wire [size-1:0] #delay y = a~^b; endmodule module param; wire [7:0] y1; wire [3:0] y2; reg [7:0] b1, c1; reg [3:0] b2, c2; modXnor G1(y1, b1, c1); modXnor #(4,5) G2(y2, b2, c2); endmodule module modXnor(y, a, b); parameter size=8, delay=15; output [size-1:0] y; input [size-1:0] a, b; wire [size-1:0] #delay y = a~^b; endmodule module param; wire [7:0] y1; wire [3:0] y2; reg [7:0] b1, c1; reg [3:0] b2, c2; modXnor G1(y1, b1, c1); modXnor #(4,5) G2(y2, b2, c2); endmodule Value of a constant can be changed during compilation Don’t confuse with assigning delay to primitives Module instantiation do not have delay Primitives do not have parameters

21. ELEN 468 Lecture 421 Indirect Substitution of Parameters module param; wire [7:0] y1; wire [3:0] y2; reg [7:0] b1, c1; reg [3:0] b2, c2; modXnor G1(y1, b1, c1); modXnor G2(y2, b2, c2); endmodule module annotate; defparam param.G2.size = 4; parem.G2.delay = 5; endmodule module param; wire [7:0] y1; wire [3:0] y2; reg [7:0] b1, c1; reg [3:0] b2, c2; modXnor G1(y1, b1, c1); modXnor G2(y2, b2, c2); endmodule module annotate; defparam param.G2.size = 4; parem.G2.delay = 5; endmodule Declare a separate module where defparam is used with hierarchical pathname

22. ELEN 468 Lecture 422 Operators OperatorNumber of Operands Result Arithmetic2Binary word Bitwise2Binary word Reduction1Bit Logical2Boolean value Relational2Boolean value Shift1Binary word Conditional3Expression

23. ELEN 468 Lecture 423 Arithmetic Operators 2’s complement representation MSB is sign bit For scalar and vector For nets and registers SymbolOperator +Addition -Subtraction *Multiplication /Division %Modulus

24. ELEN 468 Lecture 424 Bitwise Operators ~(101011) = 010100 (010101) & (001100) = 000100 (010101) ^ (001100) = 011001 ~(101011) = 010100 (010101) & (001100) = 000100 (010101) ^ (001100) = 011001 SymbolOperator ~Bitwise negation &Bitwise and |Bitwise inclusive or ^Bitwise exclusive or ~^, ^~Bitwise exclusive nor Shorter word will extend to the size of longer word by padding bits with “0”

25. ELEN 468 Lecture 425 Reduction Operators Unary operators Return single-bit value SymbolOperator &Reduction and ~&Reduction nand |Reduction or ~|Reduction nor ^Reduction xor ~^, ^~Reduction xnor &(101011) = 0 |(001100) = 1 &(101011) = 0 |(001100) = 1

26. ELEN 468 Lecture 426 Logical Operators Case equality operators detect exact bit-by-bit match, including “x” or “z” The logical equality operator is less restrictive, “x” is returned for any ambiguity Verilog is loosely typed - OK to use A&&B when A and B are vectors A&&B returns true if both words are positive integers === can recognize ‘x’ and ‘z’ while == would return ‘x’ for ambiguity SymbolOperator !Logical negation &&Logical and ||Logical or ==Logical equality !=Logical inequality ===Case equality !==Case inequality

27. ELEN 468 Lecture 427 Relational and Shift Operators Relational operators return ‘x’ for ambiguity 0xxx > 1xxx returns 1 if ( ( a = c ) ) result = a << 3; if ( ( a = c ) ) result = a << 3; Relational operatorsShift operators <<< <=>> > >=

28. ELEN 468 Lecture 428 Conditional Operator Y = ( A == B ) ? C : D; wire [1:0] select; wire [15:0] D1, D2, D3, D4; wire [15:0] bus = (select == 2’b00) ? D1 : (select == 2’b01) ? D2 : (select == 2’b10) ? D3 : (select == 2’b11) ? D4 : 16’bx Y = ( A == B ) ? C : D; wire [1:0] select; wire [15:0] D1, D2, D3, D4; wire [15:0] bus = (select == 2’b00) ? D1 : (select == 2’b01) ? D2 : (select == 2’b10) ? D3 : (select == 2’b11) ? D4 : 16’bx “z” is not allowed in conditional_expression If conditional_expression is ambiguous, both true_expression and false_expression are evaluated bitwisely according to the truth table to get the result ? :01X 00XX 1X1X XXXX

29. ELEN 468 Lecture 429 Operands A Verilog operand may be compose of Nets Registers Constants Numbers Bit-select of a net or a register Part-select of a net or a register A function call Concatenation of any of above

30. ELEN 468 Lecture 430 Operator Precedence Operator precedenceOperator symbol Highest- ! ~ (unary) * / % + - (binary) > >= == != === !== & ~& ^ ^~ ~^ | ~| && || Lowest? : Parentheses for precaution !