1. Pipelined Processor II (cont’d) CPSC 321
Andreas Klappenecker

2. Pipelined Datapath
Pipeline separation registers, width varies

3. Control Lines Instruction fetch:
control signal to read instruction memory and to write PC are always asserted - nothing special here
Instruction decode/register file read:
same thing happens every clock cycle, so no optional control lines to set
Execution/address calculation
RegDst selects the result register,
ALUOp selects the ALU operation
ALUSrc selects Read data 2 or sign-extd. immediate

4. Pipelined Datapath with Control Signals

5. Control Lines Memory access Write back Branch set by branch equal
MemRead set by load instructions
MemWrite set by store instructions
Write back
MemtoReg send ALU result or memory value
RegWrite selects register

6. Pipelined Datapath with Control Signals

7. Pipeline Control
Pass control signals along just like the data

8. Datapath with Control

9. Data Hazards
Assume that the compiler has to guarantee that no hazards occur
Where do we insert the “nops” ?
sub $2, $1, $3 and $12, $2, $5 or $13, $6, $2 add $14, $2, $2 sw $15, 100($2)

10. Dependencies
Data hazard: a dependency that “goes backward in time”

11. Forwarding

12. Forwarding

13. Obstructions to Forwarding
Load word can still cause a hazard: an instruction trying to read a register following a load instruction writing to the same register.
Need a hazard detection unit to “stall” pipeline

14. Hazard Detection Unit
Stall by letting an instruction that won’t write anything go forward

15. Branch Hazards
When we decide to branch, other instructions are in the pipeline!
We are predicting “branch not taken”
need to add hardware for flushing instructions if we are wrong

16. Flushing Instructions

17. Dynamic Scheduling The hardware performs the “scheduling”
hardware tries to find instructions to execute
out of order execution is possible
speculative execution and dynamic branch prediction
All modern processors are very complicated
DEC Alpha 21264: 9 stage pipeline, 6 instruction issue
PowerPC and Pentium: branch history table
Compiler technology important
This class has given you the background you need to learn more - read Chapter 6!
More material will be posted!