1. HEP2005, Lisboa 21-27 July 05 Roberto Campagnolo - CERN 1 HEP2005 International Europhysics Conference on High Energy Physics ( Lisboa-Portugal, 21-27 July 2005 ) Readout Electronics for the ALICE Time Projection Chamber Roberto Campagnolo – CERN PH-ED Outline: The ALICE TPC FEE Design Requirements Overview of the main Components Measurements Conclusions

2. HEP2005, Lisboa 21-27 July 05 Roberto Campagnolo - CERN 2 510 cm E E 88μs 400 V / cm The ALICE Time Projection Chamber layout GAS VOLUME: 88 m 3 90% Ne - 10%CO 2 114 556 cm LARGE DATA VOLUME : 570 132 (pads) x 1000 (time bins) 712 Mbytes / event Pb – Pb (@200 Hz)  142 Gbyte / s p-p (@1KHz)  712 GByte / s READOUT PLANE SEGMENTATION : 18 trapezoidal sectors per side each covering 20 degrees in azimuth

3. HEP2005, Lisboa 21-27 July 05 Roberto Campagnolo - CERN 3 ALICE TPC FEE – Design Requirements No. of channels :570 132 ( 1 MIP = 4.8fC, S/N = 30:1, Dynamic = 30 MIP ) Dynamic range :10 bits Sampling rate (shaping time ~ 190ns) :10 MHz No. samples / channel (drift time ~88 µs):1000 Zero suppr. data ( = 15%) :108 MByte / event L1 (start digitization) rate:~ 200 Hz Tail cancellation within 1  s (minimize pile-up) :~ 1‰ Power consumption (detector ΔT =± 0.1 ºC ) :< 100 mW / channel Tolerance to Radiation Single Event Effects

4. HEP2005, Lisboa 21-27 July 05 Roberto Campagnolo - CERN 4 ALICE TPC Readout organization and components Inner chamber Outer chamber FEC P1 : 18 FECs P6 : 20 FECs P4 : 20 FECs P3 : 18 FECs P2 : 25 FECs P5 : 20 FECs 36 Sectors, 6 Partition each

5. HEP2005, Lisboa 21-27 July 05 Roberto Campagnolo - CERN 5 ALICE TPC Readout organization and components 36 Sectors, 6 Partition each Example of Partition equipped with FECs, Readout Backplane and RCU RCU Ethernet ( 1 MB/s ) Detector Data Link ( 200 MB / s ) COUNTING ROOM ALTRO bus (2 x 200 MB/s) Local Slow-Control (2 x 2Mb/s) ON DETECTOR 1 13 2 14 12 Up-to 25 DCS int. SIU int. (DDL-SIU) Trigger int. (TTC-RX) PASA – ADC – DIG. DETECTOR TTC optical Link (Clock, L1 and L2 ) ALTRO Bus Interface Data assembler Data Acquisition RORC Detector Control System Timing, Trigger and Control Partition Architecture : 128 ch-FEC Slow Control Interface Inner chamber Outer chamber FEC P1 : 18 FECs P6 : 20 FECs P4 : 20 FECs P3 : 18 FECs P2 : 25 FECs P5 : 20 FECs

6. HEP2005, Lisboa 21-27 July 05 Roberto Campagnolo - CERN 6 The ALICE TPC Front End Card (4356 units in total) 17 cm 19 cm Pre-Ampli Shaper 10Ms/s 10bitADC Digital Circuit 8 PASA CHIPS ( 16 CH / CHIP ) 8 ALTRO CHIPS ( 16 CH / CHIP ) 128 Channels anode wire Pad plane drift region 88  s DETECTOR 570132 PADS gating grid Multi event buffer Baseline correction, Tail Cancellation, Zero supression GTL bus-transceivers Board Supply And Monitoring Board Controller (FPGA) CUSTOM IC (CMOS 0.35  m) CUSTOM IC (CMOS 0.25  m )

7. HEP2005, Lisboa 21-27 July 05 Roberto Campagnolo - CERN 7 The Pre Amplifier – Shaper Amplifier  AMS 0.35  m – Die area : 18 mm 2  Gain : 12mV / fC  FWHM : 190ns  Noise : 566e ( @ 12pF )  INL : < 0.3 %  Crosstalk : ≤ 0.1 %  Power : 11 mW / channel  Produced 49350 chips, Yield 83% CfRfCfRf (RC) 4 + - Q/C f Q OPA C f //R f CSA SHA OA 16 CH – PASA MAIN CHARACTERISTICS PASA RESPONSE FUNCTION FWHM = 190 ns Q = 149 fC A(t /  ) 4 e -4(t/  ) [ns] IN OUT [ADC]

8. HEP2005, Lisboa 21-27 July 05 Roberto Campagnolo - CERN 8 The ALiceTpcReadOut chip MAX SAMPLING CLOCK 25 MHz MAX READOUT CLOCK 60 MHz  Process: ST 0.25 µm HCMOS7 ( 6M transistor )  Online baseline correction / tail cancellation  800 k-bits internal memory  Single Event Upset-proof redundant control  area: 64 mm 2  power: 16 mW / ch  Resolution: 9.7 ENOB  Readout BW: 300 MB/s  49 000 pieces produced - Yield 84 % 16-CH Signal Digitizer and Processor

9. HEP2005, Lisboa 21-27 July 05 Roberto Campagnolo - CERN 9 ALICE TPC Readout Control Unit (216 units in total) 23 cm SIU DCS Interface Ethernet Detector Data Link TTC optical Link (Data Acquisition) (Detector Control System) (Timing, Trigger and Control ) 13.5 cm ( 200 MB / s ) ( 1 MB / s ) RCU Functions: Readout related:Slow Control related: Configuration of the ALTROs Supervision and monitoring : (via the DDL or the DCS)- Configure the power state of the FECs Distribution of the trigger and clock signals- Temperature, Current and Voltage variations (from the TTCrx)- Read status parameters (L1 and L2 counters…) FEC data readout and transfer to the DAQ - Interrupt and error handling via the DDL by the ALTRO bus (VME-like custom bus) by the Local Slow Control bus (I 2 C-like custom bus)

10. HEP2005, Lisboa 21-27 July 05 Roberto Campagnolo - CERN 10 ALICE TPC Readout Electronics - Measurements Average Noise: ~ 0.68 ADC counts (r.m.s.) ≈ 730 e - [TDR: <1000e - ] Time bin ADC Counts System Noise Tail Cancellation Filter and Moving Average Filter effects High Multiplicity Event in Field Cage Prototype ( 5500 FEE channels ) Typical Pulse shape

11. HEP2005, Lisboa 21-27 July 05 Roberto Campagnolo - CERN 11  The ALICE TPC is readout with an innovative electronics with on-detector digital signal processing.  Test performed on a sizeable fraction of the final electronics show that the system fulfills all requirements, in particular: - Power consumption : 40mW/ch - System Noise ~ 730 e - - Baseline restoration at 1 ‰ of the Dynamic Range within 1 μs  Production and test of components is on schedule for the start installation in Fall 2005 and detector commissioning in Spring 2006 Conclusions

12. HEP2005, Lisboa 21-27 July 05 Roberto Campagnolo - CERN 12 End of presentation

13. HEP2005, Lisboa 21-27 July 05 Roberto Campagnolo - CERN 13 Digital Conditioning of the TPC signal INPUT SIGNALAFTER 1 st BASELINE CORRECTION AFTER TAIL CANCELLATION AFTER 2 nd BASELINE CORRECTION

14. HEP2005, Lisboa 21-27 July 05 Roberto Campagnolo - CERN 14 Single Event Functional Interrupts with Xilinx Virtex-II Pro FPGA ( Reconfiguration started after 200 seconds, errors are then continuously detected and corrected ) Test conditions –Flux = 3.7 x 10 11 protons/cm 2 /s –Reconfiguration time = 5 s Real life –Flux = 7.9 x 10 2 hadrons/cm 2 /s –Reconfiguration time = 10 ms Duty cycle: 10 11 times better in real life Readout Control Unit – Xilinx FPGA radiation tests

15. HEP2005, Lisboa 21-27 July 05 Roberto Campagnolo - CERN 15 Integration with the Detector Configuration for the Test-Beam (May 2004) and Cosmic Rays (2005) IROC in Field Cage prototype readout with: 43 FECs ( 5500 channels, ~1 % of Alice TPC ) connected to 2 RCUs by 4 branches of ALTRO readout backplanes. 2 DCS boards interfaced to the RCUs and connected to the TTC, 2 SIUs for the DDL ‘Realistic’ Power supply distribution: Wiener500 with 40 m. cables