1. PDACS Midterm Presentation Michelle Berger John Curtin Trey Griffin Aaron King Michael Nordfelt Jeffrey Whitted

2. PDACS Getting Started Finalized components –Harris Semiconductor 8-bit A/D Converter (ADC804 ) –Texas Instruments 8-bit D/A Converter (TLC7524) –National Semiconductor 16550 UART –Maxim 232 Chip –Atmel Serial DataFlash Memory (AT45D161) Established electronic log and expenditures files

3. PDACS Team Assignments A/D - D/A Team (Michelle & Aaron) Serial / GUI Team (Mike & Trey) Memory Team (John & Jeffrey) Compression (Michelle, John, & Aaron) After we obtained our components and our collective group decisions were made, we split ourselves up into three distinct teams:

4. PDACS D/A - A/D Team Progress: A/D handled by ADC0804 Test circuit indicates A/D provides expected response D/A handled by TLC7524 Test circuit indicates D/A provides expected response A/D - D/A test circuit built and provides expected response Numerous problems encountered with D/A before settling on TLC7524 chip

5. PDACS D/A Problems The DAC0830 worked correctly but its conversion rate was too slow to keep up with the A/D. The DAC0800 was a troublesome chip. –Five separate test circuits built with the 0800 –Example: one test circuit behaved correctly until the output voltage approached 0.7 volts; beyond that point the output voltage was unpredictable –Result: none of the test circuits worked correctly, so we moved to another chip

6. PDACS D/A Solutions These are possible solutions we considered for D/A: Work with resistor values to get the 0800 to work Try another chip we had just received: the TLC7524 Reduce sampling rate so the 0830 is fast enough Build our own D/A converter using discrete components We chose to try the TLC7524, which proved to be a viable solution.

7. PDACS A/D-D/A Test Circuit

8. PDACS Memory Subsystem Atmel 16-Megabit 5-volt Serial DataFlash Memory

9. PDACS Memory Subsystem Verilog module flow: Determine read, buffer write, or main memory program and set matching opcode Clock in the necessary bits one at a time Update control variables and test the edge conditions

10. PDACS Read command Buffer write command Main memory program command Memory Subsystem Opcode Page address Byte address Don’t Care [X] (10 bits) (12 bits) (10 bits) (32 bits) Opcode Don’t Care [X] Buffer address (10 bits) (12 bits) (10 bits) Opcode Page address Don’t Care [X] (10 bits) (12 bits) (10 bits)

11. PDACS Memory Subsystem Problems: Large number of values to track SCK pin To do: Test read functionality Test write functionality

12. PDACS Serial Subsystem Specs: Consists of two chips(16550 UART and Max232) and a 9-pin serial jack Pin count to the Xilinx stands at 18 Progress: Logical layout for pins and chips determined Ordering of signals for communication determined

13. PDACS Serial Subsystem To do: Xilinx control module for the 16550 UART Physical layout Testing –Interfacing with memory access module –Interfacing with the GUI

14. PDACS Serial Subsystem Picture goes here, maybe a communications diagram

15. PDACS Serial Subsystem MemoryXILINX16550Application Master Reset DSR Interrupt Check MSR DSR Active Notify GetData Data Last Block Data Set DTR DTR DTR (Data finished)DSR Max232 (Computer Ready)

16. PDACS GUI Allows user to access the serial port and download the data from the device. The GUI was developed in Visual Basic (to allow rapid development) Visual Basic allows read/writing to all control lines for serial communication.

17. PDACS GUI Future considerations: Decompresses sound files through software, output to a.wav file Allow user to play a compressed file through the Windows soundplayer.

18. PDACS Serial/GUI Integration Used a Basic Stamp II to simulate serial port activity. GUI effectively captures all serial port traffic and dumps it to a binary file. GUI is capable of setting and reading all of the necessary control lines.

19. PDACS Compression Algorithms Companding Algorithm –written in Verilog –achieves 2:1 compression ratio –very lossy DCT Algorithm –Experimented with in C –In progress

20. PDACS Breakdown of Work Michelle Berger - Compression & A/D & D/A systems John Curtin - Compression & Memory systems Trey Griffin - GUI & Serial Interface systems Aaron King - A/D & D/A systems Michael Nordfelt - GUI & Serial Interface systems Jeffrey Whitted - Memory system Division of Labor to date

21. PDACS Schedule of Work Weeks 1-3 –A/D and D/A –Compression Research –Finalize Components Weeks 4-6 –Serial Port Interface Researched/GUI Developed –Memory Module Finalized/Hardware Wrapped –A/D and D/A Developed

22. PDACS Schedule of Work Weeks 7-10 –Compression Research/XILINX Implementation –A/D and D/A Finalization –Serial Hardware Finalization Weeks 11-12 –Final System Integration –Testing –Final Presentation and Product Delivery

23. PDACS Ratings Level of difficulty –1 Coordination among team members –1 Support from the lab –1

24. PDACS And Remember… Xilinx is cool, but it’s occasionally bogus. -Scott