1. " Characterizing the Relationship between ILU-type Preconditioners and the Storage Hierarchy" " Characterizing the Relationship between ILU-type Preconditioners and the Storage Hierarchy" Diego Rivera 1, David Kaeli 1 and Misha Kilmer 2 1 Department of Electrical and Computer Engineering Northeastern University, Boston, MA {drivera, kaeli}@ece.neu.edu 2 Department of Mathematics Tufts University, Medford, MA misha.kilmer@tufts.eduwww.ece.neu.edu/students/drivera/tlg/tunlib.html ICSS Institute for Complex Scientific Software Approximate inverse preconditioner: SPAI, MR, etc. The PIN tool was used to capture cache events. LRU and random replacement policies were modeled Several matrices were evaluated. Results from four representative matrices are shown below: Plans and future work Developing a benchmark suite for evaluating how best fill-in can be used for a given memory hierarchy and application code Arriving at an algorithmic approach to select the best values of the preconditioner parameters for a given memory hierarchy Proposing a new portable ILU-type preconditioner that does dynamic matrix fill-in:  Reordering technique for improving temporal locality  Adapting the number of non-zero elements to the block’s size of the highest cache level for improving spatial locality Objective To improve the performance of preconditioners targeting sparse matrices To accelerate the memory accesses associated with these codes Motivation Prior work targeted Krylov subspace methods However, little has been done in the case of preconditioners “Nothing will be more central to computational science in the next century than the art of transforming a problem that appears intractable into another whose solution can be approximated rapidly. For Krylov subspace matrix iterations, this is preconditioning” from Numerical Linear Algebra by Trefethen and Bau (1997). Common target applications Computational time is a barrier in these applications Parallel processing can be used to lower this barrier The sparsity of the data reduces the effectiveness of direct parallel computation Preconditioners can be used to accelerate the convergence of Krylov subspace methods A drawback of these approaches is that it is difficult to choose good values for their tuning-parameters Choosing good values depends heavily on the structure of non- zero elements of the coefficient matrix In our work we have found that it depends also on the memory hierarchy machine used to compute the solution What about tuning memory access patterns of preconditioner techniques? Acknowledgement This project is supported by the National Science Foundation’s Computing and Communication Foundations Division, grant number CCF-0342555 and the Institute of Complex Scientific Software. Preconditioner Ax=b Solution to the linear system M -1 Ax=M -1 b Iterative Method Weather Simulations Turbulence problems in airplanes DNA models A (m,m) x (m) = b (m) Results for ILUD preconditioner and method GMRES, 14 possible values for each parameter (drop tolerance, diagonal compensation parameter). There are 378 possible combinations. drop tolerance, diagonal compensation parameter and tolerance ratio , , permtol ILUDP ……... drop tolerance, diagonal compensation parameter ,  ILUD level-of-fill, drop tolerance and tolerance ratio , , permtol ILUTP level-of-fill, drop tolerance ,, ILUT level-of-fill  ILU(  ) Description parametersParametersPreconditioner Target preconditioners 1 GB RAM2 GB RAMRAM All the cache levels use a pseudo-random All cache levels use a pseudo-LRU Replacement algorithm N/A1 MB 8-wayLevel 3 8MB 2-way512 KB 8-wayLevel 2 64KB 4-way for data8KB 4-way for dataLevel 1 Ultra Sparc-III 750 MHzIntel XEON 3.06 GHz Evaluation environment 0% 21% 100% 48% Numerical symmetry (NS) Torso3 Cage14 Ldoor Raefsky3 Name 0259,1564,429,042 0.481,505,78527,130,349 1.06952,20342,493,817 4.321,2001,488,768 NS/BRowsNon-zero elements Matrices Raefsky3Ldoor Cage14 Torso3 Relation numerical-symmetry/matrix-bandwidth decreases in this direction Error norm vs. 13 first duple sorted in increasing order for execution time of ILUT and GMRES DTLB DL1 L2 Ultra Sparc-III DTLB DL1 L2 L3 Intel XEON Correlation of load accesses and execution time Cost of preconditionerVs.Cost of Krylov method = Not interesting, usually easy problems Case for Xeon: cost of preconditioner domains execution time. It is desired to pay less for the preconditioner >> << Case for Ultra: cost of Krylov method domains execution time. It is desired to pay more for the preconditioner In the i th iteration of the outer loop: Data accessed but not modified The i th row Data accessed and modified Data not accessed