1. Arithmetic Logic Unit (ALU)
Discussion D7.4
Example 21

2. ALU nf = negative flag (nf=1 if y(n-1)=1
zf = zero flag (zf = 1 if y = 0)
ovf = overflow flag
cf = carry flag

3. alu.vhd -- Example 21: alu library IEEE; use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity alu is
port(
alusel : in STD_LOGIC_VECTOR(2 downto 0);
a : in STD_LOGIC_VECTOR(3 downto 0);
b : in STD_LOGIC_VECTOR(3 downto 0);
nf : out STD_LOGIC;
zf : out STD_LOGIC;
cf : out STD_LOGIC;
ovf : out STD_LOGIC;
y : out STD_LOGIC_VECTOR(3 downto 0) );
end alu;

4. alu.vhd (cont.) architecture alu of alu is begin process(a,b,alusel)
variable temp: STD_LOGIC_VECTOR(4 downto 0);
variable yv: STD_LOGIC_VECTOR(3 downto 0);
variable cfv, zfv: STD_LOGIC;
cf <= '0';
ovf <= '0';
temp := "00000";
zfv := '0';

5. alu.vhd (cont.) case alusel is when "000" => -- pass yv := a;
when "001" => a + b
temp := ('0' & a) + ('0' & b);
yv := temp(3 downto 0);
cfv := temp(4);
ovf <= yv(3) xor a(3) xor b(3) xor cfv;
cf <= cfv;

6. Overflow
Overflow = status(1)
= c xor c(N-1)
= C xor a(N-1) xor b(N-1)
xor yv(N-1);
ci ai bi si ci+1
ci = ai xor bi xor si

7. alu.vhd (cont.) when "010" => -- a - b
temp := ('0' & a) - ('0' & b);
yv := temp(3 downto 0);
cfv := temp(4);
ovf <= yv(3) xor a(3) xor b(3) xor cfv;
cf <= cfv;
when "011" => b - a
temp := ('0' & b) - ('0' & a);

8. alu.vhd (cont.) when "100" => -- NOT yv := not a;
when "101" => AND
yv := a and b;
when "110" => OR
yv := a or b;
when "111" => XOR
yv := a xor b;
when others =>
yv := a;
end case;

9. alu.vhd (cont.) for i in 0 to 3 loop
zfv := zfv or yv(i); -- zfv = '0' if all yv(i) = '0'
end loop;
y <= yv;
zf <= not zfv;
nf <= yv(3);
end process;
end alu;