Presentation is loading. Please wait.

Presentation is loading. Please wait.

Microprocessors I Time: Sundays & Tuesdays 07:30 to 8:45 Place: EE 4 ( New building) Lecturer: Bijan Vosoughi Vahdat Room: VP office, NE of Uni Office.

Similar presentations


Presentation on theme: "Microprocessors I Time: Sundays & Tuesdays 07:30 to 8:45 Place: EE 4 ( New building) Lecturer: Bijan Vosoughi Vahdat Room: VP office, NE of Uni Office."— Presentation transcript:

1 Microprocessors I Time: Sundays & Tuesdays 07:30 to 8:45 Place: EE 4 ( New building) Lecturer: Bijan Vosoughi Vahdat Room: VP office, NE of Uni Office Hours: After 16 please Vahdat@sharif.edu http://sharif.edu/~vahdat Phone: (6616) 5001 Fax: 6600 5816

2 Grading Policy Homework:15 –Subject:UPI2010:HWX:IDxxxxxxxx Quiz: 10 Mid-term Exam 25 Final Exam: 25 Final Project:25 Presenting New Materials on Microprocessors +5 Paper Discussion +5

3 Resources Microprocessors and Interfacing Douglos V. Hall 5 Volumes from Intel - Intel® 64 and IA-32 Architectures - Software Developer’s Manual –1: Basic Architecture –2A: Instruction Set A-M –2B: Instruction Set N-Z –3A, 3B: System Programming Guides

4 Reference Book

5 Text: Table of Contents 1.Computer Number Systems, Codes, and Digital Devices 2.Computers, Microcomputers, and Microprocessors —An Introduction 3.8086 Family Assembly Language Programming—Introduction 4.Implementing Standard Program Structures in 8086 Assembly Language 5.Strings, Procedures, and Macros 6.8086 Instruction Descriptions and Assembler Directives 7.8086 System Connections Timing, and Troubleshooting 8.8086 Interrupts and Interrupt Applications 9.Digital Interfacing (PPT ) 10.Analog Interfacing and Industrial Control (D/A – A/D – DSP) 11.Dma, Drams, Cache Memories, Coprocessors, and Eda Tools 12.C, a High-level Language for System Programming 13.Microcomputer System Peripherals (Keyboard –Display –HDD –Printer) 14.Data Communication and Networks ( Async – Sync –LAN - GPIB) 15.The 80286, 80386 and 80486 Microprocessors 16.An Introduction to the Pentium Processors (New Edition)

6 Covered by 5 Volums Pentium® processors P6 family processors Pentium® 4 processors Pentium® M processors Intel® Xeon® processors Pentium® D processors Extreme Editions 64-bit Xeon® processors Core TM Duo processor Core TM Solo processor Dual-Core Xeon® LV Xeon® processor 3000, 3200 Xeon® processor 5000 Intel® Core TM 2 –Duo processor –Quad Q6000 series –Extreme X7000 and X6800 –Extreme QX6000 –Extreme QX9000 - X9000 –Quad Q9000 series –Duo E8000, T9000 Intel® Xeon® 5100, 5300 series Intel® Xeon® processor 7100 Intel® Pentium® Dual-Core Xeon® processor 7200, 7300 Xeon® 5200, 5400, 7400 Atom TM processor family Intel® Core TM i7 processor

7 History: 1/4 19714004 4bit, 4K, 50KIPS4004 197280088bit, 16K 19744040 Like 4004, Higher speed 19748080Like 8008, 64K, TTL 19778085Updated 8080, 246 Instr. 19788086 Architecture from 80808086 19798088 1980 8087 Floating-point coprocessor 1981 80286 extended the 8086 (16M) – 1 st Fully Compatible with its predecessor

8 History: 2/4 198580386 32 bits data80386 198980486Containing Coprocessor 1992Pentium Superscalar ArchitechturePentium 1995Pro : 4 Instructions added to 386Pro 1997PentiumII with MMX TechnologyPentiumII 1998Pentium II Xeon 1999Celeron PPGA 1999Pentium IIIPentium III 2000 – 2006Pentium® 4 Processor FamilyPentium® 4 2001- 2007 Xeon® Processor

9 History: 3/4 2003-Current Pentium® M ProcessorPentium® M 2005-2007 Pentium® Processor Extreme Edition 2006-2007 The Intel® Core™ Duo and Intel® Core™ Solo Processors 2006-Current The Intel® Xeon® Processor 5100, 5300 Series and Intel® Core™2 Processor Family

10 History: 4/4 2007-Current The Intel® Xeon® Processor 5200, 5400, 7400 Series and Intel® Core™2 Processor Family 2008-Current The Intel® Atom™ Processor Family 2008-Current The Intel® Core™i7 Processor FamilyCore™i7

11 Where to go

12 Intel 4004 4 bit microprocessor 4KB of memory 45 instructions 50 KIPS(Kilo-instructions per second) Main problems: –Speed –word width –memory size

13 8086 / 8088 16-bit microprocessor 2.5 MIPS 1MB of memory A small 4- or 6-byte instruction cache or queue Over 20,000 variations of instructions The popularity of the Intel family ensured in 1981 by IBM

14 80386 275,000 transistors Intel’s first practical 32-bit microprocessor 32-bit data bus and memory address 4GB of memory Memory management unit Multitasking

15 Pentium P5 architecture / 80586 Introductory version: 60MHz and 66MHz, 110MIPS / 100MHz, 150MIPS 16KB of cache size (8KB IC, 8KB DC) 4GB of memory system, 64-bit data bus Executes up to two instructions at a time (If they don’t conflict!)

16 P5 Architecture

17 Pentium Pro Processor P6 architecture 5.5M Transistors, 3 integer units, floating-point unit Basic clock frequency: 150 MHz and 166MHz 16K L1 Cache(8K for data and 8K for instructions) + 256K L2 Cache Execute up to three instructions at a time (It doesn’t matter even if they conflict!)

18 P6 Architecture Three-way Superscalar, pipelined architecture

19 P6 Architecture

20 Pentium II Processor P6 architecture 7.5M Transistors Initially ran at 233MHz and 266MHz 32KB L1 Cache + 512KB L2 Cache (External → 50% of processor speed) Arranging the amount of L2 Cache → Celeron(1999) or Xeon(1998)

21 Pentium III Processor P6 architecture 9.5 Million transistors 450 and 500 MHz SSE(Streaming SIMD Extensions) instructions Improved L1 cache controller Low-end Celeron / High-end Xeon

22 Pentium 4 Processor NetBurst architecture Deep instruction pipeline, SSE2, 64-Bit floating point computation 42 Million transistors, 1.4 GHz and 1.5 GHz Hyper Threading

23 Pentium M Processor M for Mobile: Laptop Execution core of the Pentium III + Pentium 4 compatible bus interface Improved instruction decoding/issuing front end + improved branch prediction + SSE2 support a much larger cache Low average power consumption, Lower heat output than desktop

24 The Intel® Core™i7 Processor support Intel 64 architecture Based on Intel micro-architecture (Nehalem) using 45 nm process technology. Intel® Turbo Boost Technology converts thermal headroom into higher performance. Intel® HyperThreading Technology in conjunction with Quadcore to provide four cores and eight threads. Dedicated power control unit to reduce active and idle power consumption.

25 Integrated memory controller on the processor supporting three channel of DDR3 memory. 8 MB inclusive Intel® Smart Cache. Intel® QuickPath interconnect (QPI) providing point-to-point link to chipset. Support for SSE4.2 and SSE4.1 instruction sets. Second generation Intel Virtualization Technology. The Intel® Core™i7 Processor


Download ppt "Microprocessors I Time: Sundays & Tuesdays 07:30 to 8:45 Place: EE 4 ( New building) Lecturer: Bijan Vosoughi Vahdat Room: VP office, NE of Uni Office."

Similar presentations


Ads by Google