1. RIMAC: Redundancy-based hierarchical I/O cache architecture for energy-efficient, high- performance storage systems Xiaoyu Yao and Jun Wang Computer Architecture and Storage System Laboratory (CASS) University of Nebraska - Lincoln

2. 2006-04-20 University of Nebraska-Lincoln 2 Big Picture Current energy-efficient storage solutions promising:  Saving energy at the cost of performance  Saving energy by using DRPM disk New RIMAC: Redundancy-based hierarchical I/O cache architecture  Making storage cache aware of redundancy  Solving the performance problem with power aware request transformation

3. 2006-04-20 University of Nebraska-Lincoln 3 Outline Background & Motivation  Why?  How does RIMAC differ? RIMAC: Redundancy-based Hierarchical I/O Cache Architecture Evaluation Conclusion

4. 2006-04-20 University of Nebraska-Lincoln 4 Energy Issues of Internet Data Center Router Web Servers Application Servers Database Servers … … … SAN … Storage System Interne t 27% of Total Energy* * From WP’02 http://www.max-t.comhttp://www.max-t.com 70%/Year Switch

5. 2006-04-20 University of Nebraska-Lincoln 5 Backend Storage System High performance SCSI disks Small disk array as building block  RAID-1, mirrored disk array  RAID-5, parity disk array Multi-level I/O cache  Large storage cache  Moderate RAID controller cache

6. 2006-04-20 University of Nebraska-Lincoln 6 Related Work NameConventional Disk Disk Array Storage Cache Performance Penalty MAID (SC ‘02) YesRAID-0Yes PDC (ICS '04) YesNo Yes FS2 (SOSP’05) YesNo DRPM (ISCA’03) NoRAID-1 RAID-5 No PA/PB (HPCA’04) No Yes Hibernator (SOSP’05) NoRAID-5No

7. 2006-04-20 University of Nebraska-Lincoln 7 Motivations Server workload characteristics  Dispersed idle period High performance vs. energy conservation  Long “Passive spin-up” delay in conventional disks (10-15 seconds) Exploiting existing infrastructure to consolidate the short idle period  Internal redundancy in disk array  Multi-level I/O cache

8. 2006-04-20 University of Nebraska-Lincoln 8 RIMAC - Redundancy Identifying sources of “passive spin-up”  Non-blocking read  Derivative read due to parity update  Dirty block flushing [Zhu et. al. HPCA’04] Exploiting inherent redundancy to untouched sources of “passive spin-up”  1/N redundancy in RAID-5,  Requests on standby disks are transformed to active disk accesses

9. 2006-04-20 University of Nebraska-Lincoln 9 RIMAC - Cooperative Cache Deploying parity exclusive cache  Storage cache: user data  RAID controller cache: parity Leveraging redundancy exploitation in cache  High performance power-aware request transformation in multi-level I/O cache  Larger effective storage cache size with new placement/replacement algorithm

10. 2006-04-20 University of Nebraska-Lincoln 10 Sample Scenario – Transformable Read in Cache (TRC) P4 9 5 1 10 P3 6 2 11 7 P2 3 12 8 4 P1 Bottom-Half Up-Half Storage Cache Parity CacheP2P3 XOR 6 45 … Read (addr=6, len=1) FRONT-ENDFRONT-END Response Idle/Active Standby RIMAC Storage System …… Disk1Disk3Disk4Disk2

11. 2006-04-20 University of Nebraska-Lincoln 11 Sample Scenario – Transformable Read on Disk (TRD) P4 9 5 1 10 P3 6 2 11 7 P2 3 12 8 4 P1 Bottom-Half Up-Half Storage Cache Parity CacheP2P3 XOR 6 48 … Read (addr=6, len=1) FRONT-ENDFRONT-END Response Idle/Active Standby RIMAC Storage System …… Disk1Disk3Disk4Disk2

12. 2006-04-20 University of Nebraska-Lincoln 12 Power-aware Request Transformation Storage Cache Parity Cache Disks Read TRC TRD PU-DA-C PU-CA-C PU-DA-D PU-CA-D Write (PUPA)

13. 2006-04-20 University of Nebraska-Lincoln 13 PUPA - Parity Update with Power-Aware Direct Access:  P2’ = 5’ XOR 5 XOR P2 Complementary Access:  P2’ = 5’ XOR 6 XOR 4 P4 9 5 1 10 P3 6 2 11 7 P2 3 12 8 4 P1 Write (addr=5, len=1)

14. 2006-04-20 University of Nebraska-Lincoln 14 Cache Placement/Replacement Algorithms Storage Cache  LRU with N-1 constraints  Compatible with MQ, LIRS, ARC algorithm Parity Cache  Parity stripe only  Second chance replacement algorithm

15. 2006-04-20 University of Nebraska-Lincoln 15 Evaluation Trace driven simulation  Disksim 2.0  3-state disk power models (IBM 36Z15)  RIMAC front-end, bottom-half and upper-half implementation with 5000 lines of C code Workloads  Cello99 from HP: file server  TPC-D from HP: decision support  SPC-SE from SPC: search engine

16. 2006-04-20 University of Nebraska-Lincoln 16 System Performance Cello99TPC-DSPC-SE 30% 20-30%2-6%5-14% Larger cache does improve performance

17. 2006-04-20 University of Nebraska-Lincoln 17 Energy Consumption Cello99TPC-DSPC-SE 14-15% 33-34% 15-16% Larger cache may not save more energy

18. 2006-04-20 University of Nebraska-Lincoln 18 Effects of Read Policies Cello99-64 MBTPC-D 128 MBSPC-SE 256 MB 33.8% 12.8% 49.5% 10.1% 4.1% 6.9%

19. 2006-04-20 University of Nebraska-Lincoln 19 Effects of Power Aware Parity Update Policies Cello99-64 MB TPC-D 128 MB Parity Hit Ratio 83.7% 13.8%

20. 2006-04-20 University of Nebraska-Lincoln 20 Anatomy of Energy Consumption Cello99-64 MB

21. 2006-04-20 University of Nebraska-Lincoln 21 Conclusions RIMAC: Redundancy based Hierarchical I/O cache architecture with minimum overhead Address an open problem - “passive spin-up” in energy-efficient server storage systems by power-aware request transformation both in caches and on disks Reduce energy cost by up to 33% and improve performance by up to 30%

22. 2006-04-20 University of Nebraska-Lincoln 22 Thank you!