1. EMC Models

2. Summary 1. Models, what for ? 2. EMC of IC Model 3. Core Model
4. Package models
5. Emission measurements/simulations
6. Immunity measurements/simulations
7. Chip-to-chip Coupling
8. Future of EMC models
9. Conclusion
The presentation is laid out as follows: why EMC models, the definition of a macro-model for an integrated circuit, the package models, the correlation with measurements and the future of EMC models.
April 17

3. Models – What for ?
IC designers want to predict EMC before fabrication
Noise margin
Switching Noise on Vdd
IC designers want to predict power integrity and EMI during design cycle to avoid redesign
EMC models and prediction tools have to be integrated to their design flows
IC designers want to predict voltage drops inside their chips, which has to remain lower than noise margins. Moreover, as their components are submitted to EMC constraints depending on the application domain, they want also to forecast parasitic emission and vulnerability of their circuits to EMI. Therefore, they have to deal with PI and EMI problems during conception cycles, so that they have to integrate EMC models and prediction tools to their design flow. On top of it, IC designers have to be EMC concerned !
April 17

4. Models – What for ?
Equipment designers want to predict EMC before fabrication
© Siemens Automotive Toulouse
Most of the time, EMC measurements are performed once the equipment is built.
No improvements can be done at conception phase.
Predict EMC performances  IC, board, equipment optimizations
However, need of non-confidential IC models (black box models)
Equipment designers want to predict the parasitic emission of their equipment, such as the automotive engine control system shown here, by courtesy of Siemens Automotive SA. The short distance scan of the equipment shows specific areas with strong emission (In red), and other areas with low emission (in blue). Most of the time, the emission measurement is performed once the equipment is fabricated, and software tools do not predict accurately the measured emission.
Predict EMC performances allows an optimization of design of PCB and systems before fabrication. However, models of ICs used in applications are required. That’s why equipment designers ask IC manufacturers for IC models. IC manufacturers have to provide models which predicts correctly emission and immunity performances of their ICs without giving any confidential information about their technology and design techniques.
April 17

5. EMC of IC models
EMC Models depends on the targeted complexity, the level of confidentiality of information.
Level
100 V(f), 100 Z(f)
Equipment
V, Z
LEECS
ICEM
Dipoles
102 R,L,C,I
101 R,L,C,I
101 dipoles
Board
Component
Expo
PowerSI
104 R,L,C,I
Physical
106 R,L,C,I
spice
Complexity
low
medium
high
x-high
Confidentiality
April 17

6. EMC of IC model
The model of an IC can be derived from its physical architecture.
It includes the core and package model.
Model of the die :
internal activity (core)
on-chip decoupling
supply network
I/O structure
Core
Core IC
Model of the package using R,L,C
The macro-model of an IC consists of two main parts: one related to the core of the integrated circuit, the other one related to the package. Concerning the core, the internal switching activity is the main concern. The supply network also needs a careful analysis, as well as the active inputs and outputs.
Concerning the package, an R,L,C matrix representing the interconnect array is required.
Package
April 17

7. Simulated Emission spectrum
EMC of IC models
General flow to build an EMC model and predict EMC performances
Test bench Model
Test board Model
Package Model
Core – I/O Model
EMC Model for
the circuit
Simulated Emission spectrum
Electrical
Simulation
The general flow to build a model of IC and simulate EMC performances (emission or susceptibility). Concerning simulation, our task is to define a model of the board including the IC, the package, the measurement probe and the test board. Each part requires some specific model, extracted from layout, design information, technical documentation, or measurement. Typically, simulations are performed with electrical simulator (SPICE, VHDL-AMS).
April 17

8. From floorplan estimation Without IC confidential information
EMC of IC models
EMC of IC models
How establishing an EMC of IC model ?
From layout
From floorplan estimation
Without IC confidential information
Internal Activity
I(t) simulation
Estimated current source model for each block
External i(t) measurement  internal current extraction
On-chip decoupling
Layout extraction
Estimated on-chip capacitance for each block
S parameter measurements
Supply Network
RC Layout extraction
Power supply placement from datasheet
I/O
Full model of I/O
I(V) characteristic from IBIS file
Package
Measurement
3D EM simulation
IBIS package data
Objectives
Accurate prediction, check EMC performances
Feasibility study, 1st noise evaluation, optimization of on-chip and supply pairs placement
Provide model to predict EMC compliance of an entire system
info
block
April 17

9. Electromagnetic solver
Package Model S
3D Electromagnetic solver
Electromagnetic solver
S parameter black box
Method of moment
FEM
FDTD
PEEC…
Geometrical meshed model
Simulation of EM behavior of packages
Extraction of package model
Electrical models compatible with electrical simulator (SPICE-like)
Modeling the package is mandatory for EMC of IC analysis since it induces switching noise due to internal activity of the component and generates resonances at high frequency. Different techniques exist to extrat an equivalent model. The first one is based on the use of a 3D electromagnetic solver (MoM, FEM, FD-TD,PEEC). A meshed geometrical model is required for the simulation. The electromagnetic method depends on the expected format for results : time or frequency domain, S parameter box, transmission line or RLCG lumped models. Methods which provides RLCG matrix, like PEEC, are well adapted for electrical simulation flows.
RLC matrix
April 17

10. Package Model S parameters extraction Coplanar probe
Vector Network Analyzer
Package
Extraction of package model from measurement
Calibration plane issues from hundreds of MHz
Require good knowledge in RF measurement
A vector network analyzer is well adapted to extract an electrical or RLC lumped model for packages. It gives a frequency description of the electrical behaviour of the package. Another way to extract package model is TDR.
The main issue of VNA measurement is linked with the calibration plane of the equipment. It measures S parameters or input impedance of every devices placed after this plane. If the package is mounted on a board, the contributions of board and package are measured and it is difficult to remove board influence from the measurement. The best method to extract only the influence of package is the use of coplanar miniature probe.
April 17

11. Equivalent passive model Substrate, interconnections metallization
Core model
Supply network model
Complex network of interconnections, vias and on-chip capacitances
Coupling path for noise through the IC
Require extraction of impedance between Vdd and Vss.
Possible modeling by an equivalent passive model
Equivalent passive model
The IC is composed of a complex network of interconnections, via, on-chip capacitances. It creates a complex impedance structure between Vdd and Vss, which influes on the propagation of the noise inside and outside the chip. The impedance between Vdd and Vss is mainly capacitive and resistive. For large chip, an inductive contribution can be taken into account.
Substrate, interconnections metallization
Capacitive behavior
April 17

12. Extraction of internal current waveform
Core model
Model core activity : extract noise source
16 bit
processor
16 MHz
32 bit
processor
500 MHz
Extraction of internal current waveform I I
3 A
Modeling the core activity corresponds to the extraction of the noise current, by one or several equivalent current sources. Waveforms are often complex and a 1st order approximation is to model them with triangular waveforms.
100 mA
62.5 ns
time
time
2 ns
1st order assumption : model core activity by triangular waveform current source
April 17

13. Core model Model core activity: noise source
Physical Transistor level (Spice)
Huge simulation
Limited to analog blocks
Interpolated Transistor level
Difficult adaptation to usual tools
Limited to 1 M devices
Simple, not limited
Fast & accurate
Gate level Activity (Verilog)
Activity estimation from data sheet
Very simple, not limited
Immediate, not accurate
time (ns)
200
400
600
800
1000
1200 20 40 60 80
100
120
140
Activity
Equivalent
Current generator
Extraction
The modeling of the core can be performed at various levels. We illustrate here four approaches. The first one, acting at physical level, consists in the analog simulation of the core. This approach is limited to small blocks, typically 100 to 1000 transistors. The current consumed on the VDD and VSS supply lines are accurately predicted.
For large blocks, a working approach consists in the use of pseudo analog simulation, where the physical set of equations is replaced by an approximated tabulated array of data. This approach speeds up considerably the simulation, which remains at analog level, and gives the current flow on VDD and VSS almost as accurately as for the pure analog simulation. However, the supply voltages are considered perfect.
For several millions of devices, the only remaining approach is based on the gate current approximation, using a statistical approach for elementary gate current. The total current is the sum of elementary currents, each one being characterized individually under typical loading and switching conditions.
Finally, the last approach is the less accurate but the fastest method to provide a rough approximation of the internal activity. This method is based on the estimation of the activity from several basic data like the number of gates, the average activity %, the technology, clock frequency.
April 17

14. Floorplanning, physical layout
Core model
Model The IC using a complete power supply distribution network
Chip model
Package model
Package model
Floorplanning, physical layout
Chip model
Vdd2
Vss2
Vdd1
Elementary cell
Vss1
Full chip switching noise analysis, mapping of voltage drop, evaluation of power integrity, crosstalk, EMI, effect of on-chip decoupling.
Very accurate but large netlists.
Too much complex to add PCB model.
Adapted for IC designer issues.
Modeling an IC requires models of Internal activity, internal supply network and package. Predict the internal voltage drops and emission from the complete netlist of a circuit is impossible, so that equivalent electrical circuit are used.
The first approach for the EMC model of an IC consists in meshing the chip in elementary cells, which can be extracted from the floorplan, approximative power routing and pre-characterized standard cells at pre layout step. They can also be extracted from layout at backend design. These cells are composed of a equivalent current source, a lumped RLC model for supply traces. They form a power grid which is connected to the package. Typically, the model of the package is mandatory since it adds inductances which contributes to the creation of internal voltage drops.
April 17

15. Silicium voltage drop map
Core model
Model core activity: Tool example
Layout
Silicium voltage drop map
Different methodologies and commercial tools exist to model the internal core activity. These tools are able to predict quite accurately the current consumption at different place of a circuit. As the picture show, if the supply network is known, it is also possible to predict the internal voltage drop.
PowerSI - Real-time voltage noise simulation (right), including on-chip decoupling capacitors, shows a more stable on-chip power supply © Sigrity
April 17

16. Core model Model The IC using double LC system
Example of measurement of IC conducted emission
Emission Level (dBµV)
1st resonance
Envelop of spectrum
2nd resonance
This slide presents an example of conducted emission spectrum measurement. It makes appear two increases of noise emission at 30 and 500 MHz. These 2 resonances are typical of IC emission spectrums.
Frequency (MHz)
April 17

17. Core model Model The IC using double LC system ICEM model Rvdd Lvdd
Package model
IC model
Rvdd
Lvdd
External VDD
ICEM model
(IEC )
LPackVdd Cd Cb
LPackVss Ib
External VSS
Rvss
Lvss
Primary resonance
Secondary resonance
Frequency
Emission level
From the double resonance observation, ICEM model has been proposed. This model is based on a double LC system. It is composed of the IC model and the package model. These 2 LC make appear two resonances on the emission spectrum.
Low L,C values =>
High resonant frequency
April 17

18. Input driver I(V) characteristics Output driver I(V) characteristics
IO Model
IBIS: Input Buffer I/O specification
Input driver I(V) characteristics
[Component] Fx45H725
[Manufacturer] Finex
[Package]
| variable typ min max |
R_pkg 800m 500m 950m
L_pkg 6nH 5.5nH 7.5nH
C_pkg 8pF 4pF 10.5pF
[Pin] signal model R_pin L_pin C_pin
1 /1OE in m 7.25nH 10.1pF
2 1Y1 out 1 916m 7.17nH 9.94pF …
IBIS file
Output driver I(V) characteristics
Here is an example of IBIS description file, which gives some I(V) characteristics for I/Os. These data are helpful to produce equivalent models for I/Os. I/O modeling is very important for the prediction of I/O emission (model of I/O coupled with supply network model allows predicting the SSN), but also for I/O immunity prediction.
I/O switching noise prediction
I/O immunity prediction
Very important for :
April 17

19. Test bench model TEM Cell Near-field scan DPI injection
Electrical model extracted by S parameter measurements and electromagnetic simulations
Test bench models should be generic
Limited frequency range due to influence of parasitic elements, apparition of high order propagation mode
TEM Cell
DPI capacitance
Near-field scan
DPI injection
April 17

20. Time Domain Simulation
Emission measurement/simulation
Conducted/Radiated emission prediction
Simulations
Measurements
Core
Model
Elec. package
Board
DUT
IC Model 1
To receiver
Spectrum analyzer
Time Domain Simulation
FFT of Vanalyzer(t)
Compare spectrums
EMC model
Measurements
Here is a concrete example of simulation compared with measurements, using the conducted 1ohm probe. This is the same process for TEM/GTEM radiated emission measurement. The measurement is provided by a high quality frequency analyzer, and the model is given by a SPICE analog simulation in time domain, converted in the appropriate units (dBµV vs frequency) by fast Fourier transform.
April 17

21. Emission measurement/simulation
Conducted/Radiated emission prediction
dBµV
MHz
Emission spectrum
measurement
simulation
ICEM model
April 17

22. Magnetic near field scan of a 16 bit microcontroller
Emission measurement/simulation
Near field method - theory H1 H2 P
Magnetic near field scan of a 16 bit microcontroller
Vss
I(vss)
chip
I(vdd)
Vdd
Package is the main contributor of the radiated emission of an IC
Magnetic field emission is generated by the flowing of parasitic current through package pins
April 17

23. Emission measurement/simulation
Near field method – prediction principle
Scan Simulations
Scan Measurements
Spectrum analyser
H[x,y] at given f,
given z
Positionning [x,y]
Geometrical package model
Core
Model
Elec. package
Analog Time Domain Simulation
Fourier Transform of I(t)
H[x,y,z] of I(f)
Compare scans
April 17

24. Emission measurement/simulation
Near-field scan: S12X case study (144 pins, 0.25µm)
Scan area
Package model with 13 leads
Simulation of H field at 32 MHz
Measurement of H field at 32 MHz
April 17

25. Susceptibility measurement/simulation
Susceptibility prediction model
IBIS
ICEM
Time
Amplitude
Disturbance model
Coupling path model
IC model
Supply network Z(f)
I/O
Functional model
output
input
clock
Vdd
Vss
Resonance
Finally, could the ICEM model be used in susceptibility? This is still an opened question but the UTE task force in France has started a debate and technical research on this topic. The goal is to propose some enhancements in the structural description of IC models in order to predict the first order response of the IC to external electromagnetic wave.
The figure gives a global view of a susceptibility model which is composed of the disturbance model (injection device) and the IC model. Some parts of ICEM model, as the supply network are reused. IBIS can provide valuable information about I/O behavior.
ICIM draft standard (Integrated Circuit immunity Model)
Reuse of standard non-confidential models (ICEM, IBIS)
Susceptibility peaks linked with supply network anti-resonances
April 17

26. Susceptibility measurement/simulation
Susceptibility simulation flow
Aggressed IC
Model (ICEM)
Package
and IO model (IBIS)
RFI and coupling path model (Z(f))
Set RFI frequency
IC-EMC
Susceptibility threshold simulation
Increase RFI frequency
Increase V aggressor
Time domain simulation
WinSPICE
Criterion analysis
Extract forward power
IC-EMC
April 17

27. Susceptibility measurement/simulation
16 bit micro-controller I/O susceptibility prediction
16 bit micro-controller
Direct power injection
Input buffer aggression
Sinusoidal mode
Simulation criterion: Logical change of input buffer
From A. Boyer’s PhD, INSA, 2007
April 17

28. Conclusion EMC models can help earn/save money
Macro-models of ICs include core, I/O and package modeling
The core model is based on current evaluation and on-chip capacitance
The package model is based on RLC
Good prediction of emission and susceptibility up to 2 GHz
Soon, requirements up to 3-10 GHz
This presentation is now completed. We detailed how an IC design methodology including EMC modeling and prediction may help saving money. We described the structure of the IC macro-model that enabled and accurate prediction of conducted/radiated emission, through a reduced set of simple elements. Then, we explained how the model can be feed with physical data at printed circuit, package, I/O and core level. We showed interesting correlation between measurements and simulation for a conducted 1ohm and TEM cell approaches, up to 1GHz. The future of EMC models, for bandwidth up to 18GHz and susceptibility have also briefly been discussed.
April 17