1. Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Lecture 12: MOS Transistor Models Prof. Niknejad

2. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley Lecture Outline MOS Transistors (4.3 – 4.6) – I-V curve (Square-Law Model) – Small Signal Model (Linear Model)

3. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley Observed Behavior: I D -V GS Current zero for negative gate voltage Current in transistor is very low until the gate voltage crosses the threshold voltage of device (same threshold voltage as MOS capacitor) Current increases rapidly at first and then it finally reaches a point where it simply increases linearly

4. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley Observed Behavior: I D -V DS For low values of drain voltage, the device is like a resistor As the voltage is increases, the resistance behaves non-linearly and the rate of increase of current slows Eventually the current stops growing and remains essentially constant (current source) “constant” current resistor region non-linear resistor region

5. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley “Linear” Region Current If the gate is biased above threshold, the surface is inverted This inverted region forms a channel that connects the drain and gate If a drain voltage is applied positive, electrons will flow from source to drain p-type n+ p+ Inversion layer “channel” G D S NMOS

6. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley MOSFET: Variable Resistor Notice that in the linear region, the current is proportional to the voltage Can define a voltage-dependent resistor This is a nice variable resistor, electronically tunable!

7. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley Finding I D = f (V GS, V DS ) Approximate inversion charge Q N (y): drain is higher than the source  less charge at drain end of channel

8. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley Inversion Charge at Source/Drain

9. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley Average Inversion Charge Charge at drain end is lower since field is lower Simple approximation: In reality we should integrate the total charge minus the bulk depletion charge across the channel Source End Drain End

10. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley Drift Velocity and Drain Current “Long-channel” assumption: use mobility to find v Substituting: Inverted Parabolas

11. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley Square-Law Characteristics Boundary: what is I D,SAT ? TRIODE REGION SATURATION REGION

12. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley The Saturation Region When V DS > V GS – V Tn, there isn’t any inversion charge at the drain … according to our simplistic model Why do curves flatten out?

13. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley Square-Law Current in Saturation Current stays at maximum (where V DS = V GS – V Tn = V DS,SAT ) Measurement: I D increases slightly with increasing V DS model with linear “fudge factor”

14. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley Pinching the MOS Transistors When V DS > V DS,sat, the channel is “pinched” off at drain end (hence the name “pinch-off region”) Drain mobile charge goes to zero (region is depleted), the remaining elecric field is dropped across this high-field depletion region As the drain voltage is increases further, the pinch off point moves back towards source Channel Length Modulation: The effective channel length is thus reduced  higher I DS p-type n+ p+ Pinch-Off Point G D S NMOS Depletion Region

15. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley Linear MOSFET Model Channel (inversion) charge: neglect reduction at drain Velocity saturation defines V DS,SAT = E sat L = constant - v sat /  n Drain current: |E sat | = 10 4 V/cm, L = 0.12  m  V DS,SAT = 0.12 V!

16. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley Why Find an Incremental Model? Signals of interest in analog ICs are often of the form: Direct substitution into i D = f(v GS, v DS ) is tedious AND doesn’t include charge-storage effects … pretty rough approximation Fixed Bias Point Small Signal

17. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley Which Operating Region? TRIODE SAT OFF

18. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley Changing One Variable at a Time Assumption: V DS > V DS,SAT = V GS – V Tn (square law) Square Law Saturation Region Linear Triode Region Slope of Tangent: Incremental current increase

19. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley The Transconductance g m Defined as the change in drain current due to a change in the gate-source voltage, with everything else constant Gate Bias Drain Current Bias Drain Current Bias and Gate Bias

20. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley Output Resistance r o Defined as the inverse of the change in drain current due to a change in the drain-source voltage, with everything else constant Non-Zero Slope

21. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley Evaluating r o

22. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley Total Small Signal Current Transconductance Conductance

23. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley Putting Together a Circuit Model

24. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley Role of the Substrate Potential Need not be the source potential, but V B < V S Effect: changes threshold voltage, which changes the drain current … substrate acts like a “backgate” Q = (V GS, V DS, V BS )

25. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley Backgate Transconductance Result:

26. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley Four-Terminal Small-Signal Model

27. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley MOSFET Capacitances in Saturation Gate-source capacitance: channel charge is not controlled by drain in saturation.

28. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley Gate-Source Capacitance C gs Wedge-shaped charge in saturation  effective area is (2/3)WL (see H&S 4.5.4 for details) Overlap capacitance along source edge of gate  (Underestimate due to fringing fields)

29. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley Gate-Drain Capacitance C gd Not due to change in inversion charge in channel Overlap capacitance C ov between drain and source is C gd

30. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley Junction Capacitances Drain and source diffusions have (different) junction capacitances since V SB and V DB = V SB + V DS aren’t the same Complete model (without interconnects)

31. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley P-Channel MOSFET Measurement of –I Dp versus V SD, with V SG as a parameter:

32. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley Square-Law PMOS Characteristics

33. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley Small-Signal PMOS Model

34. EECS 105 Fall 2003, Lecture 12Prof. A. Niknejad Department of EECS University of California, Berkeley MOSFET SPICE Model Many “levels” … we will use the square-law “Level 1” model See H&S 4.6 + Spice refs. on reserve for details.