1. CBM DAQ and Event Selection Walter F.J. Müller, GSI, Darmstadt for the CBM Collaboration Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway, 4-6 April 2005

2. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 2 Outline CBM (very briefly)  observables  setup FEE/DAQ/Trigger  requirements  challenges  strategies

3. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 3 CBM at FAIR SIS 100 Tm SIS 300 Tm U: 35 AGeV p: 90 GeV Compressed Baryonic Matter Experiment

4. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 4 CBM Physics Topics and Observables In-medium modifications of hadrons  onset of chiral symmetry restoration at high ρ B  measure: , ,   e + e - (μ + μ - ) open charm: D 0, D ± Strangeness in matter  enhanced strangeness production  measure: K, , , ,  Indications for deconfinement at high ρ B  anomalous charmonium suppression ?  measure: D 0, D ± J/   e + e - (μ + μ - ) Critical point  event-by-event fluctuations  measure: π, K Good e/π separation Low cross sections → High interaction rates → Selective Triggers Hadron identification Vertex detector

5. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 5 CBM Setup  Radiation hard Silicon pixel/strip detectors in a magnetic dipole field  Electron detectors: RICH & TRD & ECAL: pion suppression up to 10 5  Hadron identification: RPC, RICH  Measurement of photons, π 0, η, and muons: ECAL

6. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 6 CBM and HADES All you want to know about CBM: Technical Status Report (400 p) now available under http://www.gsi.de/documents/DOC-2005-Feb-447-1.pdf

7. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 7 Meson Production in central Au+Au W. Cassing, E. Bratkovskaya, A. Sibirtsev, Nucl. Phys. A 691 (2001) 745 10 MHz interaction rate needed for 10-15 A GeV SIS300

8. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 8 A Typical Au+Au Collision Central Au+Au collision at 25 AGeV: URQMD + GEANT 160 p 170 n 360  - 330  + 360  0 41 K + 13 K - 42 K 0  10 7 Au+Au interactions/sec  10 9 tracks/sec to reconstruct for first level event selection

9. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 9 CBM Trigger Requirements In-medium modifications of hadrons  onset of chiral symmetry restoration at high ρ B  measure: , ,   e + e - open charm (D 0, D ± ) Strangeness in matter  enhanced strangeness production  measure: K, , , ,  Indications for deconfinement at high ρ B  anomalous charmonium suppression ?  measure: D 0, D ± - J/   e + e Critical point  event-by-event fluctuations  measure: π, K offline assume archive rate: few GB/sec 20 kevents/sec offline trigger trigger on high p t e + - e - pair trigger on displaced vertex drives FEE/DAQ architecture

10. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 10 Open Charm Detection Example: D 0  K -  + (3.9%; c  = 124.4  m) reconstruct tracks find primary vertex find displaced tracks find secondary vertex target first two planes of vertex detector few 100 μm 5 cm high selectivity because combinatorics is reduced

11. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 11 CBM DAQ Requirements Profile D and J/Ψ signal drives the rate capability requirements D signal drives FEE and DAQ/Trigger requirements  Problem similar to B detection, like in LHCb or BTeV (rip)  Adopted approach: displaced vertex 'trigger' in first level, like in BTeV (rip)  Additional Problem: DC beam → interactions at random times → time stamps with ns precision needed → explicit event association needed Current design for FEE and DAQ/Trigger:  Self-triggered FEE  Data-push architecture

12. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 12 Conventional FEE-DAQ-Trigger Layout Detector Cave Shack FEE Buffer L2 Trigger L1 Trigger DAQ L1 Accept L0 Trigger f bunch Archive Trigger Primitives Especially instrumented detectors Dedicated connections Specialized trigger hardware Limited capacity Limited L1 trigger latency Modest bandwidth Standard hardware

13. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 13 Limits of Conventional Architecture Decision time for first level trigger limited. typ. max. latency 4 μs for LHC Only especially instrumented detectors can contribute to first level trigger Large variety of very specific trigger hardware Not suitable for complex global triggers like secondary vertex search Limits future trigger development High development cost

14. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 14 L1 Trigger Special hardware High bandwidth The way out.. use Data Push Architecture Detector Cave Shack FEE Buffer L2 Trigger L1 Trigger DAQ L1 Accept L0 Trigger f bunch Archive Trigger Primitives Especially instrumented detectors Dedicated connections Specialized trigger hardware Limited capacity Limited L1 trigger latency Modest bandwidth Standard hardware f clock L2 Trigger Time distribution

15. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 15 L1 Trigger Special hardware High bandwidth The way out... use Data Push Architecture Detector Cave Shack FEE DAQ Archive f clock L2 Trigger

16. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 16 L1 Select Special hardware High bandwidth The way out... use Data Push Architecture Detector Cave Shack FEE DAQ Archive f clock L2 Select Self-triggered front-end Autonomous hit detection No dedicated trigger connectivity All detectors can contribute to L1 Large buffer depth available System is throughput-limited and not latency-limited Modular design: Few multi-purpose rather many special-purpose modules Use term: Event Selection

17. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 17 Front-End for Data Push Architecture Each channel detects autonomously all hits An absolute time stamp, precise to a fraction of the sampling period, is associated with each hit All hits are shipped to the next layer (usually concentrators) Association of hits with events done later using time correlation Typical Parameters:  with few 1% occupancy and 10 7 interaction rate: some 100 kHz channel hit rate few MByte/sec per channel whole CBM detector: 1 Tbyte/sec

18. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 18 Typical Self-Triggered Front-End Average 10 MHz interaction rate Not periodic like in collider On average 100 ns event spacing 051015202530 time amplitude 50 100 a: 126 t: 5.6 a: 114 t: 22.2 Use sampling ADC on each detector channel running with appropriate clock Time is determined to a fraction of the sampling period threshold

19. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 19 Toward Multi-Purpose FEE Chain PreAmp pre Filter ADC Hit Finder Hit Finder digital Filter digital Filter Backend & Driver Backend & Driver Pad GEM's PMT APD's Anti- Aliasing Filter Sample rate: 10-100 MHz Dyn. range: 8...12 bit 'Shaping' 1/t Tail cancellation Baseline restorer Hit parameter estimators: Amplitude Time Clustering Buffering Link protocol All potentially in one mixed-signal chip see talk V. Lindenstruth see talk L. Musa

20. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 20 CBM DAQ and Online Event Selection More than 50% of total data volume relevant for first level event selection Aim for simplicity Ansatz: do (almost) all processing done after the build stage Simple two layer approach: 1. event building 2. event processing Other scenarios are possible, putting more emphasis on: do all processing as early as possible transfer data only then necessary needed for D needed for J/μ usefull for J/μ STS, TRD, and ECAL data used in first level event selection

21. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 21 Logical Data Flow Concentrators: multiplex channels to high-speed links Time distribution Buffers Build Network Processing resources for first level event selection structured in small farms Connection to 'high level' selection processing

22. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 22 Bandwidth Requirements Data flow: ~ 1 TB/sec 1 st level selection: ~ 10 14-15 operation/sec Data flow: few 10 GB/sec to archive: few 1 GB/sec Moore helps Gilder helps ~ 100 Sub-Farms

23. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 23 Focus on CNet

24. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 24 Self-Triggered FEE – Output Format I FEE 1715... 6834... 13418... 13519... 123433... Output of a FEE chip is a list of hits Each hit has a timestamp plus other information Time Stamp Channel address other values: amplitudes pulse shape !! Time Stamp values can increase forever !! ? How to express absolute time efficiently ? Output of a single FEE chip

25. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 25 Handle the infinite Time Axis Time Epoch 1 Epoch 2Epoch 3 Epoch 4 (2, 137 ns) (3, 314 ns) 1. Subdivide Time in Epochs 2. Express a time relative to an epoch 3. Introduce Epoch Markers A Hit An Epoch Marker practical epoch length about 10 μs

26. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 26 Self-Triggered FEE – Output Format II FEE M1 H1715... H6834... H13418... H13519... H123433... M2 M3 H25819... Output of a FEE chip is a list of hits and epoch markers Each hit has a timestamp plus other information Record type Hit Epoch Marker Hit with effective timestamp (3, 258)

27. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 27 Self-Triggered FEE – Concentrators FEE M1 H1715... H6834... H13418... H13519... H123433... M2 M3 H25819... A concentrator merges the data streams and eliminates redundant epoch markers FEE M1 H182007... M2 H5892134... M3 H2582714... M1 H1715... H182007... H6834... H13418... H13519... H123433... M2 H5892134... M3 H25819... H2582714... Seems prudent to keep data always sorted in time timeaddress

28. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 28 FEE Data – Clusters I In many subsystems a particle causes correlated hits in physically neighboring detector cells (STS, TRD, ECAL) Depending on detector subsystem  the cluster pattern is 1d or 2d  contained in one FEE chip or not  examples in CBM: STS-MAPS: 2d contained STS-Strip:1d mostly contained TRD1d mostly contained to 2d often uncontained depending on pad geometry (varies inside → outside) RPCt.b.d. ECAL2d many uncontained Note for 2d: a 16(64) channel chip has ¾(½) of channels on perimeter !

29. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 29 FEE Data – Clusters II Usually one wants to read very low amplitude hits in the tail of a cluster  low channel hit threshold might give to much noise  → read only low amplitude hit if in neighborhood of a big one  → how to handle clusters crossing a chip border ? use two thresholds high threshold determines particle hit and region of interest RoI communicated to all relevant neighbors low amplitude hits in RoI are validated and send → this implies cross communication on CNet between FEE chips... If RoI are communicated, CNet becomes a real network !! Better name d FNet see talk V. Lindenstruth see talk L. Musa

30. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 30 Focus on BNet

31. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 31 Event Building – Alternatives Straight event-by-event approach:  data arrives on ~1000 links  ~100 byte per event and link  10 10 packets/sec to handle... Handle time intervals or event intervals  10 μs or 100 events seems reasonable Very regular and fully controlled traffic pattern:  data traffic can be scheduled to avoid network congestion  a large fraction of the switch bandwidth can be used

32. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 32 Networking I High-speed networking  high density connectors  2.5 Gbps SerDes now ~100 mW  480 Gbps InfiniBand switch on one chip  DDR and QDR link speeds will come  just wait and see Mellanox MTA47396 24 port InfiniBand switch  4x ports, 1 Gbyte/sec per port  → 96 x 2.5 Gbps SERDES  480 Gbps aggregate B/W  Single chip implementation  961 ball BGA  18 W power dissipation  Double data rate version (5 Gbps per link) in pipe....

33. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 33 Networking II TODAY:  Voltaire ISR 9288 switch  288 4x ports; non-blocking  cost today ~120 kEUR (or ~400 EUR/port)  288 GByte/sec switching bandwidth likely in a few years:  288 4x port QDR  likely same or lower cost  1152 GByte/sec switching speeds  adequate for CBM... Conclusion:  BNet switch is not a major issue

34. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 34 Focus on PNet

35. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 35 Network Characteristics Data Push Datagram's errors marked but not recovered Request/Response and Data Push Transactions errors recovered

36. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 36 L1 Event Selection Farm Layout Current working hypothesis: CPU + FPGA hybrid system (proviso follows) Use programmable logic for cores of algorithms Use CPU for the non-parallelizable parts Use serial connection fabric (links and switches) Modular design (only few board types) FPGA

37. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 37 Network Summary 5 different networks with very different characteristics  CNet medium distance, short messages, special requirements connects custom components (FEE ASICs)  TNet broadcast time (and tags), special requirements  BNet naturally large messages, Rack-2-Rack  PNet short distance, most efficient if already 'build-in' connects standard components (FPGA, SoCs)  HNet general purpose, to rest of world Ethernet PCIe,ASI,.... Custom Ethernet, Infiniband,... Whatever the implementation is, it will be called Ethernet... FEE Interfaces and CNet will be co-developed. Depends on clock/time distribution is done Potentially build with CNet components Look at emerging technologies Stay open for changes and surprises Cost efficiency is key here !! Probably uncritical

38. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 38 Algorithms Performance of L1 feature extraction algorithms is essential  critical in CBM: STS tracking + vertex reconstruction TRD tracking and Pid Look for algorithms which allow massive parallel implementation  Hough Transform Tracker needs lots of bit level operations, well suited for FPGA  Cellular Automaton tracker  Other approaches to be evaluated Co-develop tracking detectors and analysis algorithms  L1 tracking is necessarily speed optimized → more detector granularity and redundancy needed  Aim for CBM: Validate final hardware design with at least 2 trackers suitable for L1

39. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 39 Algorithms – an Example Hough Transform  assume track comes from (close to) primary vertex  map each measurement into 'Hough space'  a peak in Hough space indicates a real track  is a 'global' method  needs substantial amount of calculation to fill and analyze the histograms  Many, but very simple operations  allows massively parallel implementation

40. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 40 Hough-Transform – Implementation

41. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 41 Hough-Transform – Implementation Very suitable for implementation in programmable logic (FPGA's) Other track finder approaches, like cellular automata tracker, also under investigation

42. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 42 Interim Summary Event definition has changed:  now based on time stamps and time correlation Role of DAQ has changed:  DAQ is simply responsible to transport data from producers to consumers Role of 'Trigger' has changed:  filter events delivered by DAQ  'Online Event Selection' is better term System aspects:  'online' – 'offline' boundary blurs  more COTS ( commercial off the shelf ) components  much more modular system  much more adaptable system This is emerging technology in HEP, though baseline for ILC However: being used since many years in nuclear structure

43. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 43 Moore – quo vadis ? Will price/performance of computing continue to improve ?  What are limits of CMOS technology ?  Where are the markets ? What are market forces ? Technology  most of the gain comes from architecture anyway  conventional designs, especially x86, reach their limits Markets  end of the metal-box PC age → Laptops + PDA + all kind of dedicated boxes (Video, Games)  end of the binary compatibility age → intermediate code + 'Just in Time' Compilers (JIT) There is life after Intel x86 A lot of architectural innovation ahead

44. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 44 BlueGene vs Cell Processor CPU Cache Mem IO MemSPEMemSPE MemSPEMemSPE MemSPEMemSPE MemSPEMemSPE CPU Cache IO Mem BlueGene: 121 mm 2 ; 130 nm 2.8/5.6 DP GFlop STI Cell: 221 mm 2 ; 90 nm 256 SP GFlop 30 DP GFlop 25 GB/sec mem 78 GB/sec IO Finally presented on ISSCC 2005 SPE = Synergistic Processing ElementInternational Solid-State Circuit Conf.

45. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 45 BlueGene vs Cell Processor Developed by Sony, Toshiba and IBM Market: VIDEOGAMES Budget: 500 M$ Developed by IBM Market: national security science Budget: ~100 M$ High performance computing is driven now by embedded systems (games, video,....) → Science is a spin-off, at best... BG/L

46. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 46 STI Cell Processor 'normal' PowerPC CPU 8 Synergistic Processing Element (SPE) each with  258 kB memory  128 x 128 bit registers  4 SP floating point units  own instruction stream 32 multiply/add per clock cycle runs at > 4 GHz 221 mm 2 die size in 90 nm

47. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 47 Game Processors as Supercomputers ? Slide from CHEP'04 Dave McQueeney IBM CTO US Federal

48. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 48 CPU and FPGA paradigms merge Register ALU Control Wide Register ALU Control ALU Wide Register ALU Control ALU Conventional CPUSIMD (single instruction – multiple data) CPU Configurable Instruction Set CPU arithmetic resources configurable connection fabric PSM

49. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 49 Configurable Instruction Set Processor Example Stretch S5xxx  Hybrid design: conventional fixed instruction set part plus configurable instruction set part  C/C++ compiler analyses the kernel of algorithms generates custom instruction set generates code to use it  The promise easy of use of C/C++ performance of an FPGA Fabric is the keyword interconnected resources Stretch S5 engine from Stretch Inc. product brief

50. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 50 CPU and FPGA paradigms merge configurable logic CPU configurable logic CPU FPGA industry world view Processor industry world view A lot of innovation in the years to come Essential will be availability of efficient development tools Moore will go on ! There are the technologies There are the markets Architectural changes ahead

51. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 51 Summary Self-triggered FEE:  autonomous hit detection, time-stamping with ns presision  sparsification, hit buffering, high output bandwidth High bandwidth event building network  handle 10 MHz interaction rate in Au-Au  also cope with few 100 MHz interaction rate in p-p, p-A  likely be done in time slices or event slices L1 processor farm  feasible with PC + FPGA + Moore (needed 2014)  but look beyond todays PC's and FPGA's Efficient algorithms (10 9 tracks/sec)  co-design of critical detectors and tracking software Quite different from the current LHC style electronics Substantial R&D needed RII3-CT-2004-506078

52. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 52 The End Thanks for your attention

53. CBM Collaboration : 41 institutions, 15 countries China: Hua-Zhong Univ., Wuhan Croatia: RBI, Zagreb Cyprus: Nikosia Univ. Czech Republic: Czech Acad. Science, Rez Techn. Univ. Prague France: IReS Strasbourg Germany: Univ. Heidelberg, Phys. Inst. Univ. HD, Kirchhoff Inst. Univ. Frankfurt Univ. Kaiserslautern Univ. Mannheim Univ. Marburg Univ. Münster FZ Rossendorf GSI Darmstadt Russia: CKBM, St. Petersburg IHEP Protvino INR Troitzk ITEP Moscow KRI, St. Petersburg Kurchatov Inst., Moscow LHE, JINR Dubna LPP, JINR Dubna LIT, JINR Dubna MEPhi, Moskau Obninsk State Univ. PNPI Gatchina SINP, Moscow State Univ. St. Petersburg Polytec. U. Spain: Santiago de Compostela Uni. Ukraine: Shevshenko Univ., Kiev Hungaria: KFKI Budapest Eötvös Univ. Budapest Korea: Korea Univ. Seoul Pusan National Univ. Norway: Univ. Bergen Poland: Krakow Univ. Warsaw Univ. Silesia Univ. Katowice Portugal: LIP Coimbra Romania: NIPNE Bucharest

54. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 54 FPGA – Basic Building Block CLK F3 F2 F1 F0 XQ X D C Q LUT CLB Look-up Table just a 4x1 RAM D Flip-Flop Universal logic gate Elementary storage unit CLB = Configurable Logic Block

55. 4-6 April 2006 Topical Workshop: Advanced Instrumentation for Future Accelerator Experiments, Bergen, Norway --- Walter F.J. Müller, GSI 55 FPGA – Putting it together CLB PSM Configurable Logic Block Wiring Programmable switch matrix I/O blocks Modern FPGA's: >100.000 LUT 500 MHz