1. Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 491 - Senior Design I Lecture 2 - Verilog Fall 2006 Lab Tomorrow: Meet in 400 AEC 9AM Bring a Lab Notebook to Lab (choose a partner) HW Due Friday 9/1: Summary of serial communication Handout: “Structural Design with Verilog” Read Sections 1-5

2. ECE 491 Fall 2006Lecture 2 - Verilog Review 12 Today’s Outline  Overview: Electronic Design with FPGAs  Verilog Part 1  Language Overview  Combinational Logic Continuous Assignment Module Instantiation always blocks

3. ECE 491 Fall 2006Lecture 2 - Verilog Review 13 FPGA Design Flow Synthesis Placement Routing HDL (or Schematic) Input Configured Design Program  Synthesis  Translate HDL to hardware  Optimize & map to CLBs  Estimate timing  Placement  Map CLBs to specific locations  Routing  Determine how to interconnect CLBs  Program  Download bitstream into FPGA

4. ECE 491 Fall 2006Lecture 2 - Verilog Review 14 Hardware Description Languages  Verilog  Designed by one person at Gateway Design Automation (now part of Cadence)  Syntax similar to C  Favored by industrial designers  IEEE Standard 1364  VHDL  Designed by committee for the Department of Defense  Syntax similar to Pascal, ADA  Favored by government labs, contractors  IEEE Standard 1076 We’ll use Verilog!

5. ECE 491 Fall 2006Lecture 2 - Verilog Review 15 Verilog Overview  Important Points About Verilog  Language Details  Basic Module Syntax  Combinational Logic  Parameters  Module Instantiation  Sequential Logic  Finite State Machines

6. ECE 491 Fall 2006Lecture 2 - Verilog Review 16 Important Points about Verilog  Verilog is designed to model hardware  Hardware is parallel, so execution is parallel  Verilog code is not software!

7. ECE 491 Fall 2006Lecture 2 - Verilog Review 17 Important Points about Verilog (cont’d)  Verilog is based on event-driven simulation  Signal values change at specific time points  Each model: Activates in response to input events Creates output events to represent output changes A B C A B C delay=4 input event output event

8. ECE 491 Fall 2006Lecture 2 - Verilog Review 18 Important Points about Verilog (cont’d)  Verilog was designed as a simulation language  Synthesis added as an afterthought  Only a subset of the language supported for synthesis  Synthesis must match simulated behavior  We’ll focus mostly on the synthesis subset  Structural Descriptions - module instantiations  Behavioral Descriptions assign - continuous assignments always blocks  But, we’ll use simulation capabilities for verification  initial blocks  Delay

9. ECE 491 Fall 2006Lecture 2 - Verilog Review 19 Verilog module construct  Key building block of language  declaration - specifies a module interface Input & output ports connections to outside world “black box” model - no details about internals  body - specifies contents of "black box" behavior - what it does structure - how it's built from other "black boxes"

10. ECE 491 Fall 2006Lecture 2 - Verilog Review 110 Module - A Quick Example  Full Adder : module fulladder(a, b, cin, sum, cout); input a, b, cin; output sum, cout; assign sum = a ^ b ^ cin; assign cout = a & b | a & cin | b & cin; endmodule Ports Port Declarations Semicolon NO Semicolon Continuous Assignment Statements

11. ECE 491 Fall 2006Lecture 2 - Verilog Review 111 Comments about the First Example  Verilog describes a circuit as a set of modules  Each module has input and output ports  Single bit  Multiple bit - array syntax  Each port can take on a digital value (0, 1, X, Z)  Three main ways to specify module internals  Continuous assignment statements - assign  Concurrent statements - always  Submodule instantiation (hierarchy)

12. ECE 491 Fall 2006Lecture 2 - Verilog Review 112 Verilog Review - Language Details  Syntax - See Quick Reference Card  Major elements of language:  Lexical Elements (“tokens” and “token separators”)  Data Types and Values  Operators and Precedence

13. ECE 491 Fall 2006Lecture 2 - Verilog Review 113 Verilog Lexical Elements  Whitespace - ignored except as token separators  blank spaces  tabs  newlines  Comments  Single-line comments //  Multi-line comments /* … */  Operators- unary, binary, ternary  Unary a = ~b;  Binary a = b && c;  Ternary a = (b < c) ? b : c;

14. ECE 491 Fall 2006Lecture 2 - Verilog Review 114 Verilog Numbers  Sized numbers: '  - decimal number specifying number of bits  - base of number decimal 'd or 'D hex 'h or 'H binary ‘b or ‘B  - consecutive digits normal digits 0, 1, …, 9 (if appropriate for base) hex digitsa, b, c, d, e, f x "unknown" digit z "high-impedance" digit  Examples 4’b111112’h7af16’d255

15. ECE 491 Fall 2006Lecture 2 - Verilog Review 115 Verilog Numbers (cont'd)  Unsized numbers  Decimal numbers appearing as constants (236, 5, 15, etc.)  Bitwidth is simulator-dependent (usually 32 bits)  Negative numbers  sized numbers: '-' before size -8'd127 -3'b111  unsized numbers: '-' before first digit -233  Underline '_' can be used as a "spacer” 12'b00010_1010_011 is same as 12'b000101010011

16. ECE 491 Fall 2006Lecture 2 - Verilog Review 116 Verilog Strings  Anything in quotes is a string: "This is a string" "a / b"  Strings must be on a single line  Treated as a sequence of 1-byte ASCII values  Special characters - C-like (\)

17. ECE 491 Fall 2006Lecture 2 - Verilog Review 117 Verilog Identifiers  Starting character: alphabetic or '_'  Following characters: alpha, numeric, or '_'  Examples: george_paul  "Escaped" identifiers:  start with backslash  follow with any non-whitespace ASCII  end with whitespace character  Examples: \212net\**xyzzy**\$foo  Special notes:  Identifiers are case sensitive  Identifiers may not be reserved words

18. ECE 491 Fall 2006Lecture 2 - Verilog Review 118 Verilog Reserved Words alwaysandassignbeginbufbufif0bufif1 case casexcasezcmos deassigndefaultdefparamdisableedge elseendendcaseendfunctionendmodule endprimitiveendspecifyendtableendtaskeventfor forceforeverforkfunctionhighz0highz1ififnone initialinoutinputintegerjoinlargemacromodule mediummodulenandnegedgenmosnor not notif0notiforoutputparameterpmos posedgeprimitivepull0pull1pulldownpulluprcmos realrealtimeregreleaserepeatrnmosrpmosrtran rtranif0rtranif1scalaredsmallspecifyspecparamstrong0 strong1supply0supply1tabletasktimetrantranif0 tranif1tritri0tri1triandtriortriregvectored waitwandweak0weak1whilewireworxnor xor

19. ECE 491 Fall 2006Lecture 2 - Verilog Review 119 Verilog Data Types  nets - describe “wire” connections  general purpose: wire  special purpose: supply0, supply1, tri0, tri1, triand, trior, trireg, wand, wor  registers - variables (assigned values by procedural statement)  reg - basic binary values  integer - binary word (≥32 bits - machine dependent)  real - floating point (not supported by synthesis)  time - simulation time (not supported in synthesis)  realtime - simulation time (not supported in synthesis)

20. ECE 491 Fall 2006Lecture 2 - Verilog Review 120 More about Data Types  Vectors - Multiple-Bit Signals (net or register) wire [31:0] sum; reg [7:0] avg;  Arrays - used for memories reg [7:0] memory [0:255]; word size memory size

21. ECE 491 Fall 2006Lecture 2 - Verilog Review 121 Verilog Logic Values  Each wire or register type can take on 4 values:  0 - Standard binary “FALSE”  1 - Standard binary “TRUE”  X - UNKNOWN  Z - High Impedance  During simulation, all variables originally X  Complication: x & z sometimes used as “wildcards” (e.g. casex, casez )

22. ECE 491 Fall 2006Lecture 2 - Verilog Review 122 Operators and Precedence  Override with parentheses () when needed

23. ECE 491 Fall 2006Lecture 2 - Verilog Review 123 Verilog Module Declaration  Describes the external interface of a single module  Name  Ports - inputs and outputs  General Syntax: module modulename ( port1, port2,... ); port1 direction declaration; port2 direction declaration; reg declarations; wire declarations; module body - “parallel” statements endmodule // note no semicolon (;) here!

24. ECE 491 Fall 2006Lecture 2 - Verilog Review 124 Verilog Body Declaration - “Parallel” Statements  Parallel statements describe concurrent behavior (i.e., statements which “execute” in parallel)  Types of Parallel Statements:  assign - used to specify simple combinational logic  always - used to specify repeating behavior for combinational or sequential logic  initial - used to specify startup behavior (not supported in synthesis - but useful in simulation!)  module instantiation - used for structure  … and other features useful only in simulation

25. ECE 491 Fall 2006Lecture 2 - Verilog Review 125 Full Adder Example - Again  Full Adder : module fulladder(a, b, cin, sum, cout); input a, b, cin; output sum, cout; assign sum = a ^ b ^ cin; assign cout = a & b | a & cin | b & cin; endmodule Continuous Assignment Statements

26. ECE 491 Fall 2006Lecture 2 - Verilog Review 126 Bitwise Operators  Basic bitwise operators: identical to C/C++/Java module inv(a, y); input[3:0]a; output [3:0]y; assign y = ~a; endmodule Unary Operator: NOT 4-bit Ports

27. ECE 491 Fall 2006Lecture 2 - Verilog Review 127 Reduction Operators  Apply a single logic function to multiple-bit inputs module and8(a, y); input[7:0]a; output y; assign y = &a; endmodule Reduction Operator: AND equivalent to: a[7] & a[6] & a[5] & a[4] & a[3] & a[2] & a[2] & a[2] & a[0]

28. ECE 491 Fall 2006Lecture 2 - Verilog Review 128 Conditional Operators  Like C/C++/Java Conditional Operator module mux2(d0, d1, s, y); input[3:0]d0, d1; inputs; output [3:0]y; assign y = s ? d1 : d0; // output d1 when s=1, else d0 endmodule

29. ECE 491 Fall 2006Lecture 2 - Verilog Review 129 More Operators  Equivalent to C/C++/Java Operators  Arithmetic: + - * / &  Comparison: == != >=  Shifting: >  Example: module adder(a, b, y); input[31:0]a, b; output[31:0]y; assign y = a + b; endmodule  Warning: small expressions can make big hardware!

30. ECE 491 Fall 2006Lecture 2 - Verilog Review 130 Bit Manipulation: Concatenation  { } is the concatenation operator module adder(a, b, y, cout); input[31:0]a, b; output[31:0]y; output cout; assign {cout,y} = a + b; endmodule Concatenation (33 bits)

31. ECE 491 Fall 2006Lecture 2 - Verilog Review 131 Bit Manipulation: Replication  { n {pattern} } replicates a pattern n times module signextend(a, y); input[15:0]a; output [31:0]y; assign y = {16{a[15]}, a[15:0]}; endmodule Copies sign bit 16 times Lower 16 Bits

32. ECE 491 Fall 2006Lecture 2 - Verilog Review 132 Internal Signals  Declared using the wire keyword module fulladder(a, b, cin, s, cout); inputa, b, cin; output s, cout; wireprop; assign prop = a ^ b; assign s = prop ^ cin; assign cout = (a & b) | (cin & (a | b)); endmodule Important point: these statements “execute” in parallel

33. ECE 491 Fall 2006Lecture 2 - Verilog Review 133 Combinational always blocks  Motivation  assign statements are fine for simple functions  More complex functions require procedural modeling  Basic syntax: always (sensitivity-list) statement or always (sensitivity-list) begin statement-sequence end Signal list - change activates block Procedural statement ( =, if/else, etc.) Compound Statement - sequence of statements

34. ECE 491 Fall 2006Lecture 2 - Verilog Review 134 Combinational Modeling with always  Example: 4-input mux behavioral model module mux4(d0, d1, d2, d3, s, y); input d0, d1, d2, d3; input [1:0] s; output y; reg y; always @(d0 or d1 or d2 or d3 or s) case (s) 2'd0 : y = d0; 2'd1 : y = d1; 2'd2 : y = d2; 2'd3 : y = d3; default : y = 1'bx; endcase Endmodule Blocking assignments (immediate update)

35. ECE 491 Fall 2006Lecture 2 - Verilog Review 135 Another Example: ALU from ECE 313 module alu(ctl, a, b, result, zero); input[2:0]ctl; input[31:0]a, b; output[31:0]result; outputzero; reg [31:0]result; reg zero; always @(a or b or ctl) begin case (ctl) 3'b000 : result = a & b; // AND 3'b001 : result = a | b; // OR 3'b010 : result = a + b; // ADD 3'b110 : result = a - b; // SUBTRACT 3'b111 : if (a < b) result = 32'd1; else result = 32'd0; //SLT default : result = 32'hxxxxxxxx; endcase if (result == 32'd0) zero = 1; else zero = 0; end endmodule ALU zero

36. ECE 491 Fall 2006Lecture 2 - Verilog Review 136 Modeling with Hierarchy  Create instances of submodules  Example: Create a 4-input Mux using mux2 module  Original mux2 module: module mux2(d0, d1, s, y); input[3:0]d0, d1; inputs; output [3:0]y; assign y = s ? d1 : d0; endmodule

37. ECE 491 Fall 2006Lecture 2 - Verilog Review 137 Modeling with Hierarchy  Create instances of submodules  Example: Create a 4-input Mux using mux2 module module mux4(d0, d1, d2, d3, s, y); input[3:0]d0, d1, d2, d3; input[1:0]s; output [3:0]y; wire[3:0]low, high; mux2 lowmux(d0, d1, s[0], low); mux2 highmux(d2, d3, s[0], high); mux2 finalmux(low, high, s[1], y); endmodule Instance NamesConnections

38. ECE 491 Fall 2006Lecture 2 - Verilog Review 138 Data Types and Module Ports  Input ports must always be a wire (net)  Output ports can be wire or reg always @(a or b) x = a ^ b; assign y = ~a; xor(z,b,c) (instantiation) a b c x y z wire reg wire

39. ECE 491 Fall 2006Lecture 2 - Verilog Review 139 Parameterized Modules  Parameters - define values that can change  Declaration: module mod1(in1, in2, out1, out2); parameter N=default-value; input [N-1 : 0] in1, in2; output [N-1 : 0] out1; … endmodule  Instantiation: wire [7:0] w, x, y; wire z; mod1 #(8) my_mod1(w,x,y,z); Defines Parameter N Uses Parameter NSets Parameter N for instance my_mod1 Sizes must match instantiated value!

40. ECE 491 Fall 2006Lecture 2 - Verilog Review 140 Parameterized Modules: Example  N-bit 2-1 multiplexer (parameterized bitwidth) module mux2( sel, a, b, y ); parameter bitwidth=32; input sel; input [bitwidth-1:0] a, b; output [bitwidth-1:0] y; assign y = sel ? b : a; endmodule  Instantiations mux2 #(16) my16bit_mux(s, a,b, c); mux2 #(5) my5bit_mux(s, d, e, f); mux2 #(32) my32bit_mux(s, g, h, i); mux2 myDefault32bit_mux(s, j, k, l); Defines Parameter bitwidth (default value: 32 ) Uses Parameter bitwidth to set input, output size 16-bit mux 5-bit mux 32-bit mux 32-bit mux (default)

41. ECE 491 Fall 2006Lecture 2 - Verilog Review 141 Symbolic Constants with Parameters  Idea: use parameter to name “special constants” parameter RED_ALERT = 2’b11; parameter YELLOW_ALERT = 2’b01; parameter GREEN_ALERT = 2’b00;  Don’t change in module instances  Do this to make your code more understandable  For others reading your code  For yourself reading your code after some time has passed

42. ECE 491 Fall 2006Lecture 2 - Verilog Review 142 Symbolic Constant Example  7-segment decoder from Verilog Handout (Part 1) module seven_seg_display_decoder(data, segments); input[3:0]data; output[6:0]segments; reg[6:0]segments; // Segment # abc_defg hex equivalent parameterBLANK= 7’b111_1111;// h7F parameterZERO= 7’b000_0001;// h01 parameterONE = 7’b100_1111;// h4F parameterTWO= 7’b001_0010;// h12 parameterTHREE= 7’b000_0110;// h06 parameterFOUR= 7’b100_1100;// h4C parameterFIVE= 7’b010_0100;// h24 parameterSIX= 7’b010_0000;// h20 parameterSEVEN= 7’b000_1111;// h0F parameterEIGHT= 7’b000_0000;// h00 parameterNINE= 7’b000_0100;// h04

43. ECE 491 Fall 2006Lecture 2 - Verilog Review 143 Symbolic Constant Example  7-segment decoder from Verilog handout (Part 2) always @(data) case (data) 0: segments = ZERO; 1: segments = ONE; 2: segments = TWO; 3: segments = THREE; 4: segments = FOUR; 5: segments = FIVE; 6: segments = SIX; 7: segments = SEVEN; 8: segments = EIGHT; 9: segments = NINE; default: segments = BLANK; endcase endmodule

44. ECE 491 Fall 2006Lecture 2 - Verilog Review 144 Symbolic Constants using `define  Like C/C++, Verilog has a preprocessor  `define - equivalent to #define in C/C++  Symbolic constant definition: `define ZERO 7’b0000_0001  Symbolic constant usage: preface with “`” segments = `ZERO;  Other preprocessor directives  `ifdef  `else  `endif Used for conditional compilation

45. ECE 491 Fall 2006Lecture 2 - Verilog Review 145 More about always  Specifies logic with procedural statements  Simulation model: executes statements in order  Synthesized hardware: matches simulation  “ reg ” declarations  treat like variables in C or Java  assignment: holds value until a new assignment is made module my_logic(a, b, c, d); input a, b; output c, d; reg c,d; always @(a or b) begin c = a & b; d = b ^ c; end endmodule

46. ECE 491 Fall 2006Lecture 2 - Verilog Review 146 Synthesizing Comb. Logic  When no if, case, or loop statements:  Assignment statements generate logic  Outputs are values of last assignments  Logic optimized, reduced during synthesis module my_logic(a, b, c, d); input a, b; output c, d; reg c,d; always @(a or b) begin c = a & b; d = b ^ c; c = d | a; end endmodule

47. ECE 491 Fall 2006Lecture 2 - Verilog Review 147 Synthesizing Comb. Logic - if/else  if/else statements become multiplexers  multiplexers follow statement order always @(c or d or x or y) begin if (c == 1’b1) z = x + y; else z = x - y; if (d == 1’b0) w = z; else w = x; end

48. ECE 491 Fall 2006Lecture 2 - Verilog Review 148 Synthesizing Comb. Logic - if /else if / else  Each else implies mutual exclusion  if / else if / else creates a priority encoder always @(c or d or x or y) begin if (c == 1’b1) z = x + y; else if (d == 0’b0) z = x - y; else z = x; end  Use sequential if statements without else if to avoid priority if desired

49. ECE 491 Fall 2006Lecture 2 - Verilog Review 149 Synthesizing Comb. Logic - if without else  if without else : output depends on previous value always @(a or x or y) begin w = x + y; if (a == 1’b1) w = x; end  What if no previous value is specified?  Must preserve the semantics of the language  This requires a latch inference always @(a or x) begin if (a == 1’b1) w = x; end

50. ECE 491 Fall 2006Lecture 2 - Verilog Review 150 Synthesizing Comb. Logic - if without else (latch inference)  if without else : output depends on previous value always @(a or x) begin if (a == 1’b1) w = x; end  What if no previous value is specified?  Must preserve the semantics of the language  This requires a latch inference to store “old” value  Latch inferences are bad!

51. ECE 491 Fall 2006Lecture 2 - Verilog Review 151 Synthesizing Comb. Logic - case statements  Verilog case : treated as if / else if / else... always @(e or x or y) begin case (e) 2’b00 : w = x + y; 2’b01 : w = x - y; 2’b10 : w = x & y; default: w = 4’b0000; endcase end  Use default to avoid latch inference!

52. ECE 491 Fall 2006Lecture 2 - Verilog Review 152 Synthesizing Comb. Logic - One Last Pitfall  always must include all inputs in sensitivity list  OR… mismatch between synthesis & simulation! always @(e or x) begin case (e) 2’b00 : w = x + y; 2’b01 : w = x - y; 2’b10 : w = x & y; default: w = 4’b0000; endcase end Missing: or y

53. ECE 491 Fall 2006Lecture 2 - Verilog Review 153 Synthesizing Comb. Logic - One Last Pitfall  Verilog 2001 Alternative (not supported by all tools) always @* begin case (e) 2’b00 : w = x + y; 2’b01 : w = x - y; 2’b10 : w = x & y; default: w = 4’b0000; endcase end

54. ECE 491 Fall 2006Lecture 2 - Verilog Review 154 About Lab 1  Goals of Lab 1  Review Combinational Logic Design with Verilog  Learn about FPGA Design with Verilog  Learn about the Spartan-3 Starter Kit Board (S3 Board)

55. ECE 491 Fall 2006Lecture 2 - Verilog Review 155 Starter Kit Board - Overview

56. ECE 491 Fall 2006Lecture 2 - Verilog Review 156 S3 Board: Seven-Segment Display  Segment signals - active low  Digit enables used to “time multiplex” digits

57. ECE 491 Fall 2006Lecture 2 - Verilog Review 157 Using the S3 Board with Verilog  Top-level module file: s3board.v  Contains declarations for all input & output pins Switches & pushbuttons LEDs and 7-segment displays RS-232 port(s) Not used (currently): PS/2 port, VGA port  Use as a starting point for your design  Constraint file: s3board.ucf  Contains pin assignments for all inputs & outputs  Uncomment pins that you’re going to use (remove “ # ”)  These files can be downloaded from the website

58. ECE 491 Fall 2006Lecture 2 - Verilog Review 158 What to Do in Lab 1  Download “ s3board.v ” and “ s3board.ucf ”  Run ISE and create a new project  Add “ s3board.v ” and “ s3board.ucf ”  Add Verilog code for a 4-bit adder  Add Verilog code for a 7-segment decoder with hex digits  Connect slide switches to adder inputs  Connect 7-segment decoder to adder output  Connect 7-segment decoder to display LSB  Compile, download, & debug

59. ECE 491 Fall 2006Lecture 2 - Verilog Review 159 Lab 1 - Block Diagram

60. ECE 491 Fall 2006Lecture 2 - Verilog Review 160 Coming Up  Sequential Logic Design with Verilog & FPGAs