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The Control Logic Andreas Klappenecker CPSC321 Computer Architecture
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Verilog HDL
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Verilog Programming Suppose that we have a module foo Our goal is to instantiate and wire a module foon that contains n copies of the module foo. Many textbooks on Verilog suggest to write down the n instance explicitly if n = 1024 then this is not a viable option reusability of the code would be limited
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Example 1 foo foon =
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Example 1 module foo(out, a,b); output out; input a, b; xor (out, a, b); endmodule module foon(out, a, b); parameter n = 8; output [n-1:0] out; input [n-1:0] a, b; foo foon[n-1:0](out,a,b); endmodule
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Example 2 foo foon = foo
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Example 2 module foo(out, a,b); output out; input a, b; xor (out, a, b); endmodule module foon(out, a, enable); parameter n = 8; output [n-1:0] out; input [n-1:0] a; input enable; foo foon[n-1:0] (out, a, {out[n-2:0],enable}); endmodule
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Remarks The module vector operator is not available in Icarus Verilog nor in Veriwell The features shown work in vcs foo foon[n-1:0](out,a,{out[n-2:0],enable}); out and a range over [n-1:0] {out[n-2:0], enable} gives vector [n-1:0] The suggested for-loop construction does not work
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Control
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MIPS Multicycle Datapath Incomplete (branch and jumps…)
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Control What are the control signals? Finite state machine control Instruction fetch instruction decode memory reference R-type branch jump
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Multicycle Datapath and Control Lines
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High-Level Picture What happens precisely during each step of fetch/decode/execute cycles Construct the finite state control machine High-level view
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Instruction Fetch/Decode/Execute
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Instruction Fetch & Decode FSM
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Memory-Reference FSM Address calculation Load sequence read from memory store to register Access memory Store sequence write
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R-type Instruction Execution of instruction Completion of instruction
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Branch Instruction
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Implementation of FSM A FSM can be implemented by a register holding the state and a block of combinatorial logic Task of the combinatorial logic: Assert appropriate signals Generate the new state to be stored in the register
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