1. Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation
Yuanlin Lu
Intel Corporation, Folsom, CA 95630
Vishwani D. Agrawal
Department of ECE, Auburn University, Auburn, AL 36849
Jan 4-8, 2008
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Outline
Motivation
Problem Statement
Background
Proposed Technique
Statistical reduction of leakage and glitch power under process variation
Results
Conclusion
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Motivation
Leakage power has become a dominant contributor to the total power consumption
65nm, leakage is ~ 50% of total power consumption
Glitches consume 20%-70% of dynamic power
Variation of process parameters increases with technology scaling
both average and standard deviation of leakage power increase
Glitch elimination technique of path balancing becomes ineffective
Power yield and timing yield are degraded
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4. One Example: Process Variation Effect on Leakage and Performance
[Ref] S. Borkar, et. al., DAC 2003.
0.18um CMOS process
20X leakage variation
30% frequency variation
high frequency but too leaky chips must be discarded
low leakage chips with too low frequency must also be discarded
too leaky
too slow
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5. (mean-nominal)/ nominal (mean-nominal)/ nominal
Comparison of Dynamic and Leakage Power Variation of Un-Optimized C432 (1,000 Samples)
Delay
variation
(mean-nominal)/ nominal
STD / mean
10%
-0.05%
0.65%
20%
-0.07%
1.12%
30%
-0.16%
1.50%
Normalized Dynamic Power
Nominal
Leff
variation
(mean-nominal)/ nominal
STD / mean
10%
3.10%
6.1%
20%
8.75%
30.7%
30%
25.17%
112.9%
Normalized Leakage Power
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6. Process Variation and Dynamic Power
Dynamic power is normally much less sensitive to the process variation due to its approximately linear relation to process parameters.
Deterministic path balancing becomes ineffective under process variation because the perfect hazard filtering conditions can easily be corrupted with a very slight variation in process parameters.
Nominal
C432 unoptimized for glitches
C432 optimized by path balancing
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7. Previous Work and Problem Statement
Previous Work: Mixed integer linear program (MILP) for optimum Dual-Vth and delay buffer assignment for
Minimum leakage
Glitch elimination
Overall delay specification
Lu and Agrawal, “CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff,” JOLPE, vol. 2, no. 3, pp. 1-10, December 2006.
Lu and Agrawal, “Statistical Leakage and Timing Optimization for Submicron Process Variation,” Proc. 20th Int. Conf. VLSI Design, Jan. 2007, pp
Problem Statement: Minimize leakage and glitch power considering process variation.
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8. Techniques to Eliminate Glitches?
path delay difference < gate inertial delay [1] 1 2
Hazard Filtering (Gate/Transistor Sizing)
Increase gate inertial delay
Sizing gate to change gate delay
Path Balancing
Decrease path delay difference
Insert delay elements on the shorter delay signal path →3 1 2
1.5
→0.5
[1] V. D. Agrawal, International Conference on VLSI Design, 1997
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9. Glitch Elimination For every gate i:
Without process variation: | Ti – ti | ≤ Di
With process variation: Prob{ | Ti – ti | ≤ Di } ≥ η
Signal arrival time window
[ ti, Ti]
Inertial delay Di
Di = Xi Di(low Vth) + (1 – Xi) Di(high Vth), Xi = [0,1]
Leakage(i) = Xi Leajage(low Vth) + (1 – Xi) Leakage (high Vth)
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10. A Mixed Integer Linear Program for Leakage and Glitch Power Reduction
Objective function (linear approximation):
Minimize {C1·Total leakage + C2·Total glitch
suppressing delays}
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11. MILP Formulation (Deterministic vs. Statistical)
Deterministic Approach
The delay and subthreshold current of every gate are assumed to be fixed and without any effect of the process variation.
Basic MILP
– Minimize total leakage while keeping the circuit performance unchanged.
Statistical Approach
Treat delay and timing intervals as random variables with normal distributions; leakage as random variable with lognormal distribution
Basic MILP
– Minimize total nominal leakage while keeping a certain timing yield (η).
Minimize " i Î gate number
Subject to " k Î PO
Minimize " i Î gate number
Subject to " k Î PO
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12. Delay Distribution without Considering Process Variation
Circuits unoptimized for glitch
Circuits optimized for glitch by path balancing
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13. Delay Distribution under Process Variation
Circuits unoptimized for glitch
Circuits optimized for glitch by path balancing
Glitch power of unoptimized circuits is not sensitive to process variation;
Glitch power of circuits optimized by path balancing is sensitive to process variation.
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Technique of Enhancing the Resistance of Glitch Power to Process Variations
Leave a relaxed margin for process variation resistance in advance
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Results for C432
Monte Carlo Simulation (15% local process variation)
C432 optimized by the statistical MILP with greater emphasis on glitch power to process variation (blue)
C432 optimized by the deterministic MILP (Purple)
Dynamic Power
(logic simulation)
Subthreshold Leakage
(Spice simulation)
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Results of MILP: Leakage Power Distribution of Optimized Dual-Vth C7552
Mean and Standard Deviation of leakage power are reduced by the statistical method.
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Conclusion
Circuits optimized of glitch suppression can be seriously degraded by process variation.
Overdesign (3σ variation) may reduce sensitivity to process variation.
Statistical design (specified yields) can give improved tradeoffs between leakage power, glitch power and timing.
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Future Work
Iterative MILP
for dual-Vth design
Timing violations were found
The interdependency of delays of gates was neglected for simplicity in our MILP formulation.
If any timing violation is found, the new delays for all LVT cells are extracted from the current dual-Vth design and the MILP formulation is updated correspondingly. A different optimal solution is then given by the CPLEX solver with fewer timing violations. We continue iterations until all timing violations are eliminated. FF 2 3
3.2 1
8ns
LVT design
dual-Vth
design + =
8.2ns
7ns
gate delay
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19. Thank You All ! Questions?
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