1. Caltech CS184a Fall2000 -- DeHon1 CS184a: Computer Architecture (Structures and Organization) Day6: October 11, 2000 Instruction Taxonomy VLSI Scaling

2. Caltech CS184a Fall2000 -- DeHon2 Last Time Computing requirements Instruction requirements Structure

3. Caltech CS184a Fall2000 -- DeHon3 Today Instruction Taxonomy VLSI Scaling

4. Caltech CS184a Fall2000 -- DeHon4 Instruction Distribution Beyond 64 PE, instruction bandwidth dictates PE size PE area =16K   N = N (64  8 )  PE area  4  N Build larger arrays  processing elements become less dense

5. Caltech CS184a Fall2000 -- DeHon5 Instruction Memory Requirements Idea: put instruction memory in array Problem: Instruction memory can quickly dominate area, too –Memory Area = 64  1.2K  /instruction –PE area = 1M  + (Instructions)  80K 

6. Caltech CS184a Fall2000 -- DeHon6 Instruction Pragmatics Instruction requirements could dominate array size. Standard architecture trick: –Look for structure to exploit in “typical computations”

7. Caltech CS184a Fall2000 -- DeHon7 Two Extremes SIMD Array (microprocessors) –Instruction/cycle –share instruction across array of PE s –uniform operation in space –operation variance in time FPGA –Instruction/PE –assume temporal locality of instructions (same) –operation variance in space –uniform operations in time

8. Caltech CS184a Fall2000 -- DeHon8 Hybrids VLIW (SuperScalar) –Few pinsts/cycle –Share instruction across w bits DPGA –Small instruction store / PE

9. Caltech CS184a Fall2000 -- DeHon9 Architecture Instruction Taxonomy

10. Caltech CS184a Fall2000 -- DeHon10 Instruction Message Architectures fall out of: –general model too expensive –look for structure in common problems –exploit structure to reduce resource requirements Architectures can be viewed in a unified design space

11. Caltech CS184a Fall2000 -- DeHon11 VLSI Scaling

12. Caltech CS184a Fall2000 -- DeHon12 Why Care? In this game, we must be able to predict the future Rapid technology advance Reason about changes and trends re-evaluate prior solutions given technology at time X.

13. Caltech CS184a Fall2000 -- DeHon13 Why Care Cannot compare against what competitor does today –but what they can do at time you can ship Careful not to fall off curve –lose out to someone who can stay on curve

14. Caltech CS184a Fall2000 -- DeHon14 Scaling Premise: features scale “uniformly” –everything gets better in a predictable manner Parameters: –  (lambda) -- Mead and Conway (class) –S -- Bohr –1/  -- Dennard

15. Caltech CS184a Fall2000 -- DeHon15 Feature Size is half the minimum feature size in a VLSI process [minimum feature usually channel width]

16. Caltech CS184a Fall2000 -- DeHon16 Scaling Channel Length (L) Channel Width (W) Oxide Thickness (T ox ) Doping (N a ) Voltage (V)

17. Caltech CS184a Fall2000 -- DeHon17 Scaling Channel Length (L) Channel Width (W) Oxide Thickness (T ox ) Doping (N a ) 1/ Voltage (V)

18. Caltech CS184a Fall2000 -- DeHon18 Effects? Area Capacitance Resistance Threshold (V th ) Current (I d ) Gate Delay (  gd ) Wire Delay (  wire ) Power

19. Caltech CS184a Fall2000 -- DeHon19 Area   L * W    m  m 50% area 2x capacity same area

20. Caltech CS184a Fall2000 -- DeHon20 Area Perspective [2000 tech.] 18mm  18mm 0.18  m 60G 

21. Caltech CS184a Fall2000 -- DeHon21 Capacitance Capacitance per unit area –C ox =  SiO 2 /T ox –T ox  T ox /  –C ox  C ox

22. Caltech CS184a Fall2000 -- DeHon22 Capacitance Gate Capacitance –C gate = A*C ox –   –C ox  C ox –C gate  C gate / 

23. Caltech CS184a Fall2000 -- DeHon23 Threshold Voltage

24. Caltech CS184a Fall2000 -- DeHon24 Threshold Voltage V TH  V TH 

25. Caltech CS184a Fall2000 -- DeHon25 Current Saturation Current –I d =(  C OX /2)(W/L)(V gs -V TH ) 2 –V gs= V  V  –V TH  V TH  –W  W  –C ox  C ox –I d  I d 

26. Caltech CS184a Fall2000 -- DeHon26 Gate Delay  gd =Q/I=(CV)/I V  V  I d  I d  C  C /   gd  gd / 

27. Caltech CS184a Fall2000 -- DeHon27 Resistance R=  L/(W*t) W  W  L, t similar R  R

28. Caltech CS184a Fall2000 -- DeHon28 Wire Delay  wire =R L C R  R C  C /   wire  wire …assuming (logical) wire lengths remain constant...

29. Caltech CS184a Fall2000 -- DeHon29 Power Dissipation (Static) Resistive Power –P=V*I –V  V  –I d  I d  –P  P  

30. Caltech CS184a Fall2000 -- DeHon30 Power Dissipation (Dynamic) Capacitive (Dis)charging –P=(1/2)CV 2 f –V  V  –C  C /  –P  P   Increase Frequency? –f  f ? –P  P  

31. Caltech CS184a Fall2000 -- DeHon31 Effects? Area 1/   Capacitance 1/  Resistance  Threshold (V th ) 1/  Current (I d ) 1/  Gate Delay (  gd ) 1/  Wire Delay (  wire ) 1 Power 1/    1/  

32. Caltech CS184a Fall2000 -- DeHon32 Delays? If delays in gates/switching? If delays in interconnect? Logical interconnect lengths?

33. Caltech CS184a Fall2000 -- DeHon33 Delays? If delays in gates/switching? –Delay reduce with 1/ 

34. Caltech CS184a Fall2000 -- DeHon34 Delays Logical capacities growing Wirelengths? –No locallity  –Rent’s Rule L  n (p-0.5) [p>0.5]

35. Caltech CS184a Fall2000 -- DeHon35 Capacity Rent: IO=C*N p p>0.5 A  C*N 2p Logical Area     A  C*N 2 2p   N 2p  N 2 2p  N 2   p) N Sanity Check –p=1 –N 2  N –p~0.5 –N 2   N

36. Caltech CS184a Fall2000 -- DeHon36 Compute Density Density = compute / (Area * Time)   >compute density scaling>     gates dominate, p<0.5    moderate p, good fraction of gate delay    large p (wires dominate area and delay)

37. Caltech CS184a Fall2000 -- DeHon37 Power Density P  P   (static, or increase frequency) P  P   (dynamic, same freq.)   P/A  P/A … or … P/  A

38. Caltech CS184a Fall2000 -- DeHon38 Physical Limits Doping? Features?

39. Caltech CS184a Fall2000 -- DeHon39 Physical Limits Depended on –bulk effects doping current (many electrons) mean free path in conductor –localized to conductors Eventually –single electrons, atoms –distances close enough to allow tunneling

40. Caltech CS184a Fall2000 -- DeHon40 Finishing Up...

41. Caltech CS184a Fall2000 -- DeHon41 Big Ideas [MSB Ideas] Instruction organization induces a design space (taxonomy) for programmable architectures Moderately predictable VLSI Scaling –unprecedented capacities/capability growth for engineered systems –change –be prepared to exploit –account for in comparing across time

42. Caltech CS184a Fall2000 -- DeHon42 Big Ideas [MSB-1 Ideas] Uniform scaling reasonably accurate for past couple of decades Area increase   –Real capacity maybe a little less? Gate delay decreases (1/  ) Wire delay not decrease, maybe increase Overall delay decrease less than (1/  )