1. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Overview n Why VLSI? n Moore’s Law. n The VLSI design process. These lecture notes include my annotations, changes and additions. These annotations, changes, and additions marked in red are not in any way endorsed or approved by the author or publisher of the text, Modern VLSI Design/System-on-Chip Design. A. Yavuz Oruc, University of Maryland, College Park, MD 20742

2. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Why VLSI? n Integration improves the design and fabrication: –lower parasitics (capacitive charging, resistive dissipation) = higher speed; –lower power (smaller devices+ less heat dissipation at the interface); –physically smaller. n Integration reduces manufacturing cost-(almost) no manual assembly. n Integration also increases system reliability by reducing component interface and interconnections

3. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR VLSI and you n Microprocessors: –personal computers; –microcontrollers. –Hand-held devices-wireless phones, pdas,video cameras,etc… n DRAM/SRAM Memory chips n Special-purpose processors.

4. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Moore’s Law n Gordon Moore: co-founder of Intel n Predicted that number of transistors per chip would grow exponentially (double every 18 months). n Exponential improvement in technology is a natural trend: steam engines, dynamos, automobiles.

5. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Moore’s Law(Cont’d) n Q(n) = 2  Q(n-1.5) => n Q(n) = 2 k  Q(n-1.5k), n Q(0) = Q 0 (some initial value at some initial date) => k= n/1.5 and n Q(n) = Q 0  2 n/1.5 = Q 0  2 n/1.5 n = Q 0  (1.333) n n If we replace 1.5 by 1 we get a much steeper rise (2 n ). (Count doubles every year…)

6. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Moore’s Law(Cont’d)

7. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Moore’s Law(Cont’d) ftp://download.intel.com/museum/Moores_Law/Printed_Materials/Moores_Law_Backgrounder.pdf For a more complete list of intel processors and their features, see http://en.wikipedia.org/wiki/List_of_Intel_microprocessors

8. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Moore’s Law(Cont’d)

9. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Moore’s Law plot Log # transistors This is a log plot--- Taking the log of the formula for Q(n) gives a linear relation between the years and log of number of transistors: Log Q(n) = Log Q 0 + n  Log 1.333 (See slide 5)

10. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR The cost of fabrication n Current cost: $2-3 billion. n Typical fab line occupies about 1 city block, employs a few hundred people. n Most profitable period is first 18 months-2 years.

11. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Cost factors in ICs n For large-volume ICs: –packaging is largest cost; –testing is second-largest cost. n For low-volume ICs, design costs may swamp all manufacturing costs.

12. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR The VLSI design process n May be part of larger product design. n Major levels of abstraction: –specification; (describe functionality) –architecture; (describe functionality with building blocks) –logic design; (convert architecture to logic circuits) –circuit design; (convert logic logic circuits to transistor circuits) –layout. (lay out the transistor circuits in VLSI)

13. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Challenges in VLSI design n Multiple levels of abstraction: transistors to CPUs. n Multiple and conflicting constraints: low cost and high performance are often at odds. n Short design time: Late products are often irrelevant.

14. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Dealing with complexity n Divide-and-conquer: limit the number of components you deal with at any one time. n Group several components into larger components: –transistors form gates; –gates form functional units; –functional units form processing elements; –etc.

15. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Hierarchical name n Interior view of a component: –components and wires that make it up. n Exterior view of a component = type: –body; –pins. Full adder a b cin sum cout

16. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Instantiating component types n Each instance has its own name: –add1 (type full adder) –add2 (type full adder). n Each instance is a separate copy of the type: Add1(Full adder) a b cin sum cout Add2(Full adder) a b cin sum Add1.a Add2.a

17. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR z box1box2x A hierarchical logic design Incomplete--- not enough labels to specify the netlist and component list on the next slide (Component terminal counts do not appear to match either!)

18. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Net lists and component lists n Net list: (list of terminals in a net) net1: top.in1 in1.in net2: i1.out xxx.B topin1: top.n1 xxx.xin1 topin2: top.n2 xxx.xin2 botin1: top.n3 xxx.xin3 net3: xxx.out i2.in outnet: i2.out top.out n Component list (nets connected to each pin of a component): top: in1=net1 n1=topin1 n2=topin2 n3=topin3 out=outnet i1: in=net1 out=net2 xxx: xin1=topin1 xin2=topin2 xin3=botin1 B=net2 out=net3 i2: in=net3 out=outnet

19. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR A hierarchical logic design top ABC i2 o2 o1 Inserted & modified the labels i1 o1 o2 i1 i2 i1 o1 p qr s t i1o1 N

20. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Net lists and component lists Two-level net list: Level-1has 2 components, top and C, which appear on 6 nets: net11: top.p net12: top.q net13: top.r net14: top.s, C.i1 net15: top.t C.i2 net16: C.o1 Level-2 has 3 components: A, N and B, which appear on 7 nets net21: top.p, A.i1 net22: top.q, A.o2 net23: top.r, B.i2 net24: top.s, B.o1 net25: top.t, B.o2 net26: A.o1, N.i1 net27: B.i1, N.o1 Two-level component list Level-1 has 2 components, top and C and they are on the following nets: top = net11, net12, net13,net14,net15 C= net15, net16 Level-2 has 3 components, A, N, and B, and they are on the following nets A = net21, net22 B = net23, net24, net25 N = net26, net27

21. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Component hierarchy top i1xxxi2

22. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Hierarchical names n Typical hierarchical name: –top/i1.foo component pin

23. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Layout and its abstractions n Layout for dynamic latch: (Top view)

24. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Stick diagram

25. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Transistor schematic

26. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Mixed schematic inverter

27. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Levels of abstraction n Specification: function, cost, etc. n Architecture: large blocks. n Logic: gates + registers. n Circuits: transistor sizes for speed, power. n Layout: determines parasitics.

28. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Circuit abstraction n Continuous voltages and time:

29. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Digital abstraction n Discrete levels, discrete time: 1 + 1 = 2 Least significant bit

30. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Register-transfer abstraction n Abstract components, abstract data types: + + 0010 0001 0100 0111

31. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Top-down v.s. bottom-up design n Top-down design adds functional detail. –Create lower levels of abstraction from upper levels. n Bottom-up design creates abstractions from low-level behavior. n Good design needs both top-down and bottom-up efforts.

32. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Design abstractions specification behavior register- transfer logic circuit layout English Executable program Sequential machines Logic gates transistors rectangles Throughput, design time Function units, clock cycles Literals, logic depth Nanoseconds power microns functioncost

33. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Design validation n Must check at every step that errors haven’t been introduced-the longer an error remains, the more expensive it becomes to remove it. n Forward checking: compare results of less- and more-abstract stages. n Back annotation: copy performance numbers to earlier stages.

34. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Manufacturing test n Not the same as design validation: just because the design is right doesn’t mean that every chip coming off the line will be right. n Must quickly check whether manufacturing defects destroy function of chip. n Must also speed-grade.

35. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Homework Set-1 (Due: September 19) Problem 1.1. At the Intel site, http://www.intel.com/pressroom/kits/quickrefyr.htm, the clock speeds of intel family of microprocessors from 1971 to 2004 are listed. Use this list to fit the clock speeds of Intel microprocessors that were manufactured between 1971 and 2004 by a power function, i.e., determine the base b in f 0  b n, where f 0 is the clock speed in MHz in 1971 and n denotes a year between 1971 and 2004. if more than one processor is listed within a given month, use the clock speed of the fastest processor. Plot the actual clock speeds v.s. the power function you have derived. Problem 1.2. Give the net and component lists for the following circuit by clearly marking each of the nets and components. input-1 input-2 output VsVs VsVs VdVd A BC D