1. 1 MIPS תיאור מפושט של מעבד החיבורים המתוארים תומכים בכל שלבי פקודות R-type ו- I-type אנו נתמוך בפקודות: add, sub, or, xor, and, slt, lw, sw, beq, j כמובן שנצטרך לדעת כיצד מוסיפים פקודות נוספות כמו למשל: bne, addi, jal, jr

2. 2 עוד שלושה שבועות

3. 3 שלבי ביצוע הוראת מכונה (1) FETCH = קרא הוראה מהזיכרון ע " פ הכתובת שמכיל ה -PC. (2) DECODE = פענח את הפקודה וקרא את האוגרים הנחוצים ( אחד או שניים ). (3) EXECUTE = בעזרת ה -ALU חשב את התוצאה, או כתובת רצויה. (4) MEMORY = השתמש בתוצאה לבצע במידת הצורך : או טעינה לזיכרון (Store) או קריאה מהזיכרון (Load). (5) WRITE BACK = בצע במידת הצורך טעינה לאוגר.

4. 4 במשך כל מחזור השעון קוראים בסוף השעון כותבים cycle time rising edge falling edge קווי הבקרה - מיוצרים על פי השעון, כל עליית שעון תשנה בעקבותיה את קווי הבקרה (אם נדרש)

5. 5 Single cycle data paths Processor uses synchronous logic design (a “clock”). fT 1 MHz 1 μ s 10 MHz100 ns 100 MHz10 ns 1 GHz1 ns All state elements act like positive edge- triggered flip flops. DQ clk

6. 6 Edge-Triggered D Flip Flops DQ CLK Value of D is sampled on positive clock edge. Q outputs sampled value for rest of cycle. D Q

7. 7 Single cycle data paths: Definition All instructions execute in a single cycle of the clock (positive edge to positive edge) Advantage: a great way to learn CPUs. Drawbacks: unrealistic hardware assumptions, slow clock period

8. 8 Recall: MIPS R-format instructions Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction Fetch next inst from memory:012A4020 opcodersrtrdfunctshamt Decode fields to get : ADD $8 $9 $10 “Retrieve” register values: $9 $10 Add $9 to $10 Place this sum in $8 Prepare to fetch instruction that follows the ADD in the program. Syntax: ADD $8 $9 $10Semantics: $8 = $9 + $10

9. 9 Separate Read-Only Instruction Memory 32 Addr Data 32 זכרון פקודות Reads are combinational: Put a stable address on input, a short time later data appears on output. טעינת התוכנית לזכרון לא מעניננו כרגע זכרון (מטמון) נפרד לפקודות ולנתונים (Instruction Memory & Data Memory)

10. 10 שלב 1: Straight-line Instruction Fetch 32 Addr Data 32 Instr Mem Fetching straight-line MIPS instructions requires a machine that generates this timing diagram: Why +4 and not +1? Why do we increment every clock cycle? CLK Addr DataIMem[PC + 8] IMem[PC + 4] IMem[PC] PC + 8 PC + 4PC PC == Program Counter, points to next instruction.

11. 11 New Component: Register (for PC) In later examples, we will add an “enable” input: clock edge updates state only if enable is high 32 Din Clk PC Dout 32 Built out of an array of 32 flip-flops DQ clk DQ DQ Din0 Din1 Din2 Dout0 Dout1 Dout2

12. 12 New Component: A 32-bit adder (ALU) Combinational: היציאה שווה לסכום ערכי כניסה A ו-B מלפני זמן קצר (~ ננו שניה). 32 + A B A + B 32 ALUALU A B A op B op ln(#ops) ALU: כנ"ל רק למס פונקציות רבות לפי הבורר op. Zero? Sometimes, extra outputs for use by control logic...

13. 13 Design: Straight-line Instruction Fetch CLK Addr DataIMem[PC + 8] IMem[PC + 4] IMem[PC] PC + 8 PC + 4PC Clk 32 AddrData Instr Mem 32 D PC Q 32 + 0x4 +4 in hexadecimal State machine design in the service of an ISA

14. 14 Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction Fetch next inst from memory:012A4020 opcodersrtrdfunctshamt Decode fields to get : ADD $8 $9 $10 “Retrieve” register values: $9 $10 Add $9 to $10 Place this sum in $8 Prepare to fetch instruction that follows the ADD in the program. Syntax: ADD $8 $9 $10Semantics: $8 = $9 + $10 Goal #1: An R-format single-cycle CPU Done! To continue, we need registers...

15. 15 Register files: R1 R2... R31 Why is R0 special? Q Q Q R0 - The constant 0Q clk.... 32 MUXMUX sel(rs1) 5... rd1 32 MUXMUX sel(rs2) 5... rd2 “two read ports” wd D D D En DEMUXDEMUX... sel(ws) 5 WE 32

16. 16 Register File Schematic Symbol 32 rd1 RegFile 32 rd2 WE 32 wd 5 rs1 5 rs2 5 ws Why do we need WE (Write Enable)? If we had a register file w/o WE, how could we work around it?

17. 17 Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction Fetch next inst from memory:012A4020 opcodersrtrdfunctshamt Decode fields to get : ADD $8 $9 $10 “Retrieve” register values: $9 $10 Add $9 to $10 Place this sum in $8 Prepare to fetch instruction that follows the ADD in the program. Syntax: ADD $8 $9 $10Semantics: $8 = $9 + $10 Goal #1: An R-format single-cycle CPU What do we do with these?

18. 18 Computing engine of the R-format CPU 32 rd1 RegFile 32 rd2 WE 32 wd 5 rs1 5 rs2 5 ws 32 ALUALU op opcodersrtrdfunctshamt Decode fields to get : ADD $8 $9 $10 Logic What do we do with WE?

19. 19 Putting it all together... 32 rd1 RegFile 32 rd2 WE 32 wd 5 rs1 5 rs2 5 ws 32 ALUALU op Logic Is it safe to use same clock for PC and RegFile? 32 AddrData Instr Mem 32 D PC Q 32 + 0x4 To rs1, rs2, ws, op decode logic...

20. 20 Reminder: How data flows after posedge 32 rd1 RegFile 32 rd2 WE 32 wd 5 rs1 5 rs2 5 ws 32 ALUALU op Logic AddrData Instr Mem D PC Q + 0x4

21. 21 Next posedge: Update state and repeat 32 rd1 RegFile 32 rd2 WE 32 wd 5 rs1 5 rs2 5 ws D PC Q

22. 22 A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Instruction Memory PC Adde r 4 ck 6 [31:26] 6 [5:0]= funct איך זה נראה בספר?

23. 23 יחידת הרגיסטרים. יחידה זו דרושה לשלב ה-decode (ולשלב ה-write back) Read register 1 Registers Read register 2 Write register Write Data Read data1 Read data2 מספרי האוגרים Data

24. 24 Arithmetic Logic operation Read register1 Registers Read register2 Write register Write Data Read data1 Read data2 ALU Zero ALU operation ALU result Instruction ALU result ALU operation הפעולה הבסיסית שנדגים הנה פקודת R-type

25. 25 A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] 6 [5:0]= funct איך זה נראה בספר?

26. 26 A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] 6 [5:0]= funct איך זה נראה בספר?

27. 27 The internal structure of the Register File 32 Read data 2 write data Read data 1 5 5 5 Rd reg 2 (= Rt) Rd reg 1 (= Rs) RegWrite Wr reg (= Rd) 32 E קוראים משתי היציאות בוזמנית ערכים של שני רגיסטרים שונים כותבים לאחד הרגיסטרים האחרים (בעליית השעון הבאה)

28. 28 A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite

29. 29 A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCALU ck

30. 30 A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCPC ALU ck 4

31. 31 A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite 6 [5:0]=funct ALU control

32. 32 יעד מס 2: I-format ALU instructions Syntax: ORI $8 $9 64Semantics: $8 = $9 | 64 16-bit immediate extended to 32 bits.In this example, $8 (the result register) is rt !!! (was rd previously). Zero-extend: 0x8000 ⇨ 0x00008000 Sign-extend: 0x8000 ⇨ 0xFFFF8000 Some MIPS instructions zero-extend immediate field, other instructions sign- extend.

33. 33 Computing engine of the I-format CPU 32 rd1 RegFile 32 rd2 WE 32 wd 5 rs1 5 rs2 5 ws 32 ALUALU op Decode fields to get : ORI $8 $9 64 Logic In a Verilog implementation, what should we do with rs2? 32 Ext

34. 34 Merging data paths... I-format R-format “two read ports” Add muxes How many ? Where ?

35. 35 The merged data path... 32 rd1 RegFile 32 rd2 WE 32 wd 5 rs1 5 rs2 5 ws 32 ALUALU op opcodersrtrdfunctshamt ALUsrc Ext ExtOp ALUctr RegDest

36. 36 Load,Store בניית פעולות Read address Data memory Write address Write data Read data Write Read כאן נדרש זיכרון ל- data ממנו נקרא ואליו נכתוב כמו כן יש לבצע sign extension של ה- imm שהוא רק 16bit

37. 37 Loads, Stores, and Data Memory... 32 Dout Data Memory WE 32 Din 32 Addr Syntax: LW $1, 32($2)Syntax: SW $3, 12($4) Action: $1 = M[$2 + 32]Action: M[$4 + 12] = $3 Zero-extend or sign-extend immediate field? Writes are clocked: If WE is high, memory Addr captures Din on positive edge of clock. Reads are combinational: Put a stable address on Addr, a short time later Dout is ready Note: Not a realistic main memory (DRAM) model...

38. 38 איפה ה- CPU? CPU Instruction Memory Data Memory PC

39. 39 A CPU capable of lw instructions only 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite=1 16 [15:0] 5 add Sext 16->32 Data Memory Address D. Out

40. 40 A CPU capable of lw instructions only 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite=1 16 [15:0] 5 add Sext 16->32 Data Memory Address D. Out

41. 41 A CPU capable of lw & sw instructions only 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite=0 16 [15:0] 5 add Sext 16->32 Data Memory D.In Address MeWrite=1

42. 42 A CPU capable of R-type & lw instructions (principle) 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite 16 [15:0] 5 add Sext 16->32 Data Memory 5 [25:21]=Rs 6 [5:0]=funct ALU control 5 [15:11]=Rd Address

43. 43 A CPU capable of R-type & lw instructions 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite 16 [15:0] 5 add Sext 16->32 Data Memory 5 [25:21]=Rs 6 [5:0]=funct ALU control Rd Address D. Out

44. 44 A CPU capable of R-type & lw/sw instructions 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite 16 [15:0] 5 add Sext 16->32 Data Memory 5 [25:21]=Rs 6 [5:0]=funct ALU control Rd Address D.In D. Out MemWrite

45. 45 Conditional Branches in MIPS... Syntax: BEQ $1, $2, 12 Action: If ($1 != $2), PC = PC + 4 Zero-extend or sign-extend immediate field? Action: If ($1 == $2), PC = PC + 4 + 48 Immediate field codes # words, not # bytes. Why is this encoding a good idea?

46. 46 :Branch אלמנטים דרושים להוספת ALU Zero Read register1 Registers Read register2 Write register Write Data Read data1 Read data2 Instruction Adder Sum Shift left2 Sigh Extend Branch Target מועבר ליחידת הבקרה כתוצאה הלוגית של ההשוואה 1632 PC+4 משלב ה- Fetch In addresses, we always shift left by two bits

47. 47 Design: Instruction Fetch with Branch Clk 32 AddrData Instr Mem 32 D PC Q 32 + 0x4 Syntax: BEQ $1, $2, 12 Action: If ($1 != $2), PC = PC + 4 Action: If ($1 == $2), PC = PC + 4 + 48 PCSrc 32 + Ex te nd

48. 48 שילוב כל הפקודות Read register1 Registers Read register2 Write register Write Data Read data1 Read data2 Zero ALU result Data Sign extend 32 Read address memory Write address Write data Read data Write Read 16 Add 4 PC M u x Read address Instruction memory ADD ALU result Shift left2 M u x M u x

49. 49 What is single cycle control? 32 rd1 RegFile 32 rd2 WE 32 wd 5 rs1 5 rs2 5 ws Ext RegDest ALUsrc ExtOp ALUctr MemToReg MemWr Equal RegWr 32 AddrData Instr Mem Equal RegDest RegWr ExtOp ALUsrc MemWr MemToReg PCSrc Combinational Logic (Only Gates, No Flip Flops) Just specify logic functions!

50. 50 קווי בקרה PC Instruction memory Read address Instruction 16 32 Add M u x Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 4 M u x ALU operation 3 RegWrite MemRead MemWrite PCSrc ALUSrc MemtoReg ALU result Zero ALU Data memory Address Write data Read data M u x Sign extend Add ALU result Shift left 2

51. 51 Control PC Instruction memory Read address Instruction [31–0] Instruction [20–16] Instruction [25–21] Add Instruction [5–0] MemtoReg ALUOp MemWrite RegWrite MemRead Branch R register 2 Sign extend Shift left 2 M u x 1 ALU result Zero Data memory Write data Rea d dat a M u x 1 Instruction [15–11] ALU control ALU Address

52. 52 Control

53. 53 ALU control ALU control output 000 AND 001OR 010add 110subtract 111set-on-less-than (sign of rs-rt -> rd) 00 = lw, sw 01 = beq, 10 = arithmetic ALUop

54. 54 פקודת ה- jump 4 bits 26 bits 2 bits 00 : כתובת קפיצה במילים : כתובת קפיצה בבתים 0110 101 … 101111011 00 101 … 1011110110110: הקפיצה הסופית : תוספת 4 ביטים אחרונים פירוש הפקודה: J 101 … 101111011 הפקודה הבאה נמצאת בכתובת 111111011…1001

55. 55 Jump Shift left 2 PC Instruction memory Read address Instruction [31–0] Data memory Read data Write data Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Instruction [15–11] Instruction [20–16] Instruction [25–21] Add ALU result Zero Instruction [5–0] MemtoReg ALUOp MemWrite RegWrite MemRead Branch Jump RegDst ALUSrc I sult M u x 0 10 ALU Shift left 2 2628 Address