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Latches and Flip-Flops

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Presentation on theme: "Latches and Flip-Flops"— Presentation transcript:

1 Latches and Flip-Flops
Discussion D7.1

2 Latches and Flip-Flops
SR Latch D Latch Flip-Flops D Flip-Flop JK Flip-Flop T Flip-Flop

3 Sequential Logic Combinational Logic Sequential Logic
Output depends only on current input Sequential Logic Output depends not only on current input but also on past input values Need some type of memory to remember the past input values

4 Cross-coupled Inverters
State 1 State 2

5 Latches and Flip-Flops
SR Latch D Latch Flip-Flops D Flip-Flop JK Flip-Flop T Flip-Flop

6 SR Latch S' R' Q Q' 1 0 0 0 1 1 0 1 1 1 1 0 1 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

7 SR Latch S' R' Q Q' 0 0 0 1 1 0 1 1 1 1 0 1 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

8 SR Latch S' R' Q Q' 1 0 0 0 1 1 0 1 1 1 1 0 1 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

9 SR Latch S' R' Q Q' 1 0 0 0 1 1 0 1 1 1 0 Set 1 0 1 X Y nand 0 0 1
1 0 0 0 1 1 0 1 1 1 0 Set 1 0 1 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

10 SR Latch S' R' Q Q' 1 1 0 0 0 1 1 0 1 1 1 0 Set 1 0 1 Store 1 0 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

11 SR Latch S' R' Q Q' 1 1 0 0 0 1 1 0 1 0 Set 1 1 0 1 Store 1 0 X Y nand
0 0 0 1 1 0 1 1 1 0 Set 0 1 Store 1 0 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

12 SR Latch S' R' Q Q' 1 1 0 0 0 1 1 0 1 1 1 0 Set 1 0 1 Store 1 0 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

13 SR Latch S' R' Q Q' 1 0 0 0 1 1 0 1 0 Set 1 1 0 1 Reset 1 0 1 Store
0 0 0 1 1 0 1 1 1 0 Set 0 1 Reset 1 0 1 Store 1 0 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

14 SR Latch S' R' Q Q' 1 0 0 0 1 1 0 1 1 1 0 Set 0 1 Reset 1 1 0 1 Store
0 0 0 1 1 0 1 1 1 0 Set 0 1 Reset 1 1 0 1 Store 1 0 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

15 SR Latch S' R' Q Q' 1 0 0 1 1 Disallowed 0 1 1 0 1 0 Set 1 1 0 1 Reset
1 0 0 0 1 1 0 1 1 1 1 Disallowed 1 0 Set 0 1 Reset 1 0 1 Store 1 0 Q0 Q0' X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

16 SR Latch S' R' Q Q' 1 0 0 0 1 1 0 1 1 1 1 Disallowed 1 0 Set 0 1 Reset
0 0 0 1 1 0 1 1 1 1 Disallowed 1 0 Set 0 1 Reset 1 1 0 1 Store 1 0 Q0 Q0' X Y nand 0 0 1 0 1 1 1 0 1 1 1 0 To close or lock with or as if with a latch, To catch or fasten

17 SR Latch with Enable S R EN S' R' Q Q' 0 0 1 1 1 Q0 Q0' Store
Reset Set Disallowed X X Q0 Q0' Store

18 RS Latch RS Latch R S Q Q is set to 1 when S is asserted, and remains unchanged when S is disasserted. Q is reset to 0 when R is asserted, and remains unchanged when R is disasserted. Assertions can be active HIGH or active LOW

19 R Q RS Latch S Active HIGH library IEEE; use IEEE.STD_LOGIC_1164.all;
entity rslatch is port( R : in STD_LOGIC; S : in STD_LOGIC; Q : out STD_LOGIC ); end rslatch; architecture rslatch of rslatch is begin process(R,S) if S = '1' and R = '0' then Q <= '1'; elsif S = '0' and R = '1' then Q <= '0'; end if; end process; RS Latch R S Q Active HIGH

20 RS Latch -- Active High

21 R Q RS Latch S Active LOW library IEEE; use IEEE.STD_LOGIC_1164.all;
entity rslatch is port( R : in STD_LOGIC; S : in STD_LOGIC; Q : out STD_LOGIC ); end rslatch; architecture rslatch of rslatch is begin process(R,S) if S = '0' and R = '1' then Q <= '1'; elsif S = '1' and R = '0' then Q <= '0'; end if; end process; RS Latch R S Q Active LOW

22 RS Latch -- Active Low

23 How can you make this RS latch from gates?
Q Q is set to 1 when S is asserted, and remains unchanged when S is disasserted. Q is reset to 0 when R is asserted, and remains unchanged when R is disasserted. Assertions can be active HIGH or active LOW

24 Q is set to 1 when S is asserted (1), and remains unchanged when S is disasserted (0).
Q is reset to 0 when R is asserted (1), and remains unchanged when R is disasserted (0). R S Q Q R SQ 00 01 11 10 1 store 1 1 1 set 1 reset store Q = R'Q + R'S + SQ RS Latch R S Q

25 RS Latch Q = R'Q + R'S + SQ R S Q Q 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1
store set reset store RS Latch R S Q Q = R'Q + R'S + SQ

26 use IEEE.STD_LOGIC_1164.all; entity rslatchgates is port(
library IEEE; use IEEE.STD_LOGIC_1164.all; entity rslatchgates is port( R : in STD_LOGIC; S : in STD_LOGIC; Q : out STD_LOGIC ); end rslatchgates; architecture rslatchgates of rslatchgates is signal Q1: std_logic; begin Q1 <= (not R and Q1) or (not R and S) or (S and Q1); Q <= Q1; Q1

27

28 Latches and Flip-Flops
SR Latch D Latch Flip-Flops D Flip-Flop JK Flip-Flop T Flip-Flop

29 D Latch D Latch D EN Q Q follows D when EN is high, and remains unchanged when EN is low..

30 D Q D Latch EN library IEEE; use IEEE.STD_LOGIC_1164.all;
entity dlatch is port( D : in STD_LOGIC; EN : in STD_LOGIC; Q : out STD_LOGIC ); end dlatch; architecture dlatch of dlatch is begin process(D,EN) if EN = '1' then Q <= D; end if; end process; D Latch D EN Q

31 D Latch

32 D Latch S S' R' R S R EN Q Q' D EN Q Q' 0 0 1 Q0 Q0' Store 0 1 0 1
Reset Set Disallowed X X 0 Q0 Q0' Store X 0 Q0 Q0' D EN Q Q'

33 D Latch S S' R' R D EN Q Q' Note that Q follows D when EN in high,
X 0 Q0 Q0' D EN Q Q' Note that Q follows D when EN in high, and is latched when EN goes to zero.

34 Latches and Flip-Flops
SR Latch D Latch Flip-Flops D Flip-Flop JK Flip-Flop T Flip-Flop

35 D Flip-Flop D gets latched to Q on the rising edge of the clock.
clk D Q Q' X 0 Q0 Q0' D clk Q Q' Positive edge triggered D gets latched to Q on the rising edge of the clock. Behavior if rising_edge(clk) then Q <= D; end if;

36 D Q clk Q' library IEEE; use IEEE.STD_LOGIC_1164.all;
entity dflipflop is port( D : in STD_LOGIC; clk : in STD_LOGIC; Q : out STD_LOGIC; NotQ : out STD_LOGIC ); end dflipflop; architecture dflipflop of dflipflop is signal QS: STD_LOGIC; begin process(D,clk) if rising_edge(clk) then QS <= D; end if; end process; Q <= QS; NotQ <= not QS; clk D Q Q'

37 D Flip-Flop

38 D Q clk Q' library IEEE; use IEEE.STD_LOGIC_1164.all;
entity dflipflop is port( D : in STD_LOGIC; clk : in STD_LOGIC; Q : out STD_LOGIC; NotQ : out STD_LOGIC ); end dflipflop; architecture dflipflop of dflipflop is signal QS: STD_LOGIC; begin process(D,clk) if clk'event and clk = '1' then QS <= D; end if; end process; Q <= QS; NotQ <= not QS; clk D Q Q'

39 D Flip-Flop

40 Master-Slave D Flip-Flop

41 Master-Slave D Flip-Flop

42 Recall the SR Latch S' R' Q Q' 1 0 0 1 1 Disallowed 0 1 1 0 1 0 Set
1 0 0 0 1 1 0 1 1 1 1 Disallowed 1 0 Set 0 1 Reset 1 0 1 Store 1 0 Q0 Q0' X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

43 Edge-triggered D Flip-flop
1 1 1 1

44 Edge-triggered D Flip-flop
1 1 1 1 1

45 Edge-triggered D Flip-flop
1 1 1 1 1

46 Edge-triggered D Flip-flop
1 1 1 1

47 Edge-triggered D Flip-flop
1 1 1 1

48 Edge-triggered D Flip-flop
1 1 1 1 1

49 Edge-triggered D Flip-flop
1 1 1 1 1

50

51 Spartan 3 CLB slices

52 Latches and Flip-Flops
SR Latch D Latch Flip-Flops D Flip-Flop JK Flip-Flop T Flip-Flop

53 J-K Flip-flops J K Qnext Q Q' Qnext = JQ' + K'Q

54 J-K Flip-flops J K Qnext Q Q'

55 Latches and Flip-Flops
SR Latch D Latch Flip-Flops D Flip-Flop JK Flip-Flop T Flip-Flop

56 T Flip-flops T Qnext 0 Q 1 Q'

57 T Flip-flops T Qnext 0 Q 1 Q'

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