1. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt1 Lecture 19alt I DDQ Testing (Alternative for Lectures 21 and 22) n Definition n Faults detected by I DDQ tests n Weak fault n Leakage fault n Sematech and other studies n Delta I DDQ testing n Built-in current (BIC) sensor n Summary

2. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt2 Basic Principle of I DDQ Testing n Measure I DDQ current through V ss bus

3. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt3 NAND Open Circuit Defect – Floating gate

4. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt4 Floating Gate Defects n Small break in logic gate inputs (100 – 200 Angstroms) lets wires couple by electron tunneling  Delay fault and I DDQ fault n Large open results in stuck-at fault – not detectable by I DDQ test  If V tn < V fn < V DD - | V tp | then detectable by I DDQ test

5. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt5 Delay Faults n Many random CMOS defects cause a timing delay fault, not catastrophic failure n Some delay faults detected by I DDQ test – late switching of logic gates keeps I DDQ elevated n Delay faults not detected by I DDQ test  Resistive via fault in interconnect  Increased transistor threshold voltage fault

6. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt6 Weak Faults n nFET passes logic 1 as 5 V – V tn n pFET passes logic 0 as 0 V + |V tp | n Weak fault – one device in C-switch does not turn on  Causes logic value degradation in C-switch

7. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt7 Weak Fault Detection n Fault not detected unless I3 = 1

8. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt8 Leakage Fault n Leakage between bulk (B), gate (G), source (S) and drain (D) n Leakage fault table for an MOS component: n k = number of component I/O pins n n = number of component transistors n m = 2 k (number of I/O combinations) n m x n matrix M represents the table n Each I/O combination is a matrix row n Entry m i j = octal leakage fault information:  Flags f BG f BD f BS f SD f GD f GS  Sub-entry m i j = 1 if leakage fault detected

9. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt9 Leakage Fault Table

10. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt10 I DDQ Vector Selection n Characterize each logic component using switch-level simulation – relate input/output logic values & internal states to:  leakage fault detection  weak fault sensitization and propagation n Store information in leakage and weak fault tables n Generate complete stuck-at fault tests n Logic simulate stuck-at fault tests – use tables to find faults detected by each vector to select vectors for current measurement

11. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt11 Com- pany HP San- dia Reject ratio (%) Without I DDQ With I DDQ Without I DDQ With I DDQ Neither 16.46 0.80 Only Funct. 6.36 0.09 Only Scan 6.04 0.11 Both 5.80 0.00 Functional Tests 5.562 0 Scan and Functional Tests HP and Sandia Lab Data n HP – static CMOS standard cell, 8577 gates, 436 FF n Sandia Laboratories – 5000 static RAM tests n Reject ratio (%) for various tests:

12. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt12 Failure Distribution in Hewlett-Packard Chip

13. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt13 Sematech Study n IBM Graphics controller chip – CMOS ASIC, 166,000 standard cells 0.8  m static CMOS, 0.45  m Lines (L eff ), 40 to 50 MHz Clock, 3 metal layers, 2 clocks n Full boundary scan on chip n Tests:  Scan flush – 25 ns latch-to-latch delay test  99.7 % scan-based stuck-at faults (slow 400 ns rate)  52 % SAF coverage functional tests (manually created)  90 % transition delay fault coverage tests  96 % pseudo-stuck-at fault cov. I DDQ Tests

14. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt14 Sematech Results n Test process: Wafer Test Package Test Burn-In & Retest Characterize & Failure Analysis n Data for devices failing some, but not all, tests. pass fail pass 14 6 52 pass 6 0 1 36 fail 1463 34 13 1251 pass fail 7 1 8 fail pass fail pass fail Scan-based Stuck-at IDDQ (5  A limit) Functional Scan-based delay

15. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt15 Sematech Conclusions n Hard to find point differentiating good and bad devices for I DDQ & delay tests n High # passed functional test, failed all others High # passed all tests, failed I DDQ > 5  A n Large # passed stuck-at and functional tests  Failed delay & IDDQ tests n Large # failed stuck-at & delay tests  Passed I DDQ & functional tests n Delay test caught failures in chips at higher temperature burn-in – chips passed at lower temperature

16. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt16 % Functional Failures After 100 Hours Life Test Work of McEuen at Ford Microelectronics

17. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt17 Current Limit Setting Should try to get it < 1  A n Histogram for 32 bit microprocessor

18. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt18 Difference in Histograms n A – test escapes, B – yield loss

19. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt19 Delta I DDQ Testing (Thibeault) n Use derivative of I DDQ at test vector i as current signature ΔI DDQ (i) = I DDQ (i) – I DDQ (i – 1) n Leads to a narrower histogram n Eliminates variation between chips and between wafers Select decision threshold Δ def to minimize probability of false test decisions

20. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt20 |I DDQ | and |  I DDQ |

21. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt21 Setting Threshold I DDQ ΔI DDQ Mean (good chips)0.696 μA-2×10 -4 μA Mean (bad chips)1.096 μA0.4 μA Variance0.039 (μA) 2 0.004 (μA) 2 Δ def Error Prob. 0.30.0597.3×10 -4 0.40.0324.4×10 -5 0.50.0171.7×10 -6

22. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt22 I DDQ Built-in Current Testing – Maly and Nigh n Build current sensor into ground bus of device-under-test n Voltage drop device & comparator  Compares virtual ground V GND with V ref at end of each clock – V GND > V ref only in bad circuits  Activates circuit breaker when bad device found

23. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt23 Conceptual BIC Sensor

24. Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 19alt24 Summary n I DDQ test is used as a reliability screen n Can be a possible replacement for expensive burn-in test n I DDQ test method has difficulties in testing of sub-micron devices  Greater leakage currents of MOSFETs  Harder to discriminate elevated I DDQ from 100,000 transistor leakage currents  I DDQ test may be a better choice n Built-in current (BIC) sensors can be useful