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May 18, 2004MS Defense: Uppalapati1 Low Power Design of Standard Cell Digital VLSI Circuits By Siri Uppalapati Thesis Directors: Prof. M. L. Bushnell and.

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Presentation on theme: "May 18, 2004MS Defense: Uppalapati1 Low Power Design of Standard Cell Digital VLSI Circuits By Siri Uppalapati Thesis Directors: Prof. M. L. Bushnell and."— Presentation transcript:

1 May 18, 2004MS Defense: Uppalapati1 Low Power Design of Standard Cell Digital VLSI Circuits By Siri Uppalapati Thesis Directors: Prof. M. L. Bushnell and Prof. V. D. Agrawal ECE Department, Rutgers University

2 May 18, 2004 MS Defense: Uppalapati 2 Talk Outline Motivation Background Prior Work Proposed Design Flow Results Conclusion and Future Work

3 May 18, 2004 MS Defense: Uppalapati 3 Motivation Increasing gate count + increasing clock frequency = increasing POWER Portable equipment runs on battery Power consumption due to glitches can be 30 – 70%

4 May 18, 2004 MS Defense: Uppalapati 4 Motivation: Chip Power Density 4004 8008 8080 8085 8086 286 386 486 Pentium® P6 1 10 100 1000 10000 19701980199020002010 Year Power Density (W/cm2) Hot Plate Nuclear Reactor Rocket Nozzle Sun’s Surface Source: Intel 

5 May 18, 2004 MS Defense: Uppalapati 5 Motivation (cont’d…) Present day Application Specific Integrated Circuit (ASIC) chips employ standard cell based design style A quick way to design circuits with millions of gates Existing glitch reduction techniques demand gate re-design: not suitable for a cell-based design

6 May 18, 2004 MS Defense: Uppalapati 6 Problem Statement To devise a glitch suppressing methodology after the technology mapping phase Without requiring cell re- design Without violating circuit delay constraints Design Entry Technology Mapping Layout

7 May 18, 2004 MS Defense: Uppalapati 7 Talk Progress Motivation Background Prior Work Proposed Design Flow Results Conclusion and Future Work

8 May 18, 2004 MS Defense: Uppalapati 8 Power Dissipation in CMOS Circuits (0.25µ) %75%5%20 P total = C L V DD 2 f 0  1 + t sc V DD I peak f 0  1 + V DD I leakage CLCL

9 May 18, 2004 MS Defense: Uppalapati 9 Glitches? Unnecessary transitions Occur due to differential path delays Contribute about 30-70% of total power consumption Delay =1 2 2

10 May 18, 2004 MS Defense: Uppalapati 10 Standard Cell Based Style Standard cells organized in rows (and, or, flip-flops, etc.) Cells made as full custom All cells of same height Reasonable design time Due to automatic translation from logic level to layout Routing Cell IO cell

11 May 18, 2004 MS Defense: Uppalapati 11 Talk Progress Motivation Background Prior Work Proposed Design Flow Results Conclusion and Future Work

12 May 18, 2004 MS Defense: Uppalapati 12 Prior Work Existing glitch reduction techniques Low power design by hazard filtering [Agrawal, VLSI Design ’97] Reduced constraint set linear program [Raja et al., VLSI Design ’03] CMOS circuit design for minimum dynamic power and highest speed [Raja et. al., VLSI Design ’04] Optimization of cell based design Cell library optimization [Masgonty et al., PATMOS ’01] Cell selection [Zhang et al., DAC ’01)]

13 May 18, 2004 MS Defense: Uppalapati 13 Prior Work: Hazard Filtering Glitch is suppressed when the inertial delay of gate exceeds the differential input delays. Re-design all gates in the circuit for inertial delay > differential delay 3 2 Filtering Effect of a gate Reference: V. D. Agrawal, “Low Power Design by Hazard Filtering”, VLSI Design 1997

14 May 18, 2004 MS Defense: Uppalapati 14 Prior Work: A Reduced Constraint Set LP Model for Glitch Removal Gate variables d 4..d 12 Buffer Variables d 15..d 29 Corresponding window variables t 4..t 29 and T 4..T 29. Reference: T. Raja, V. D. Agrawal and M. L. Bushnell, “Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program”, VLSI Design ‘2003

15 May 18, 2004 MS Defense: Uppalapati 15 Prior Work: A Reduced Constraint Set LP Model for Glitch Removal (cont’d…) Objective function: Minimize sum of buffer delays inserted Glitch removal constraint: Maxdelay constraint: Transistor sizing or other procedures used to implement these delays d g > T g – t g all gates g Objective: minimize Σ d j all buffers j T PO > maxdelay

16 May 18, 2004 MS Defense: Uppalapati 16 Prior Work: Cell Library Optimization Limited logic functions with greater cell sizing can result in 20 - 25% savings in power Transistor sizing for Multiple driving strength Balanced rise and fall times Power optimized by minimizing parasitic capacitances Limitations: Discrete set of varieties Optimization of cells cannot be circuit-specific Reference: J. M. Masgonty, S. Cserveny, C. Arm and P. D. Pfister, “Low-Power Low- Voltage Standard Cell Libraries with a Limited Number of Cells”, PATMOS ‘01

17 May 18, 2004 MS Defense: Uppalapati 17 Prior Work: Cell Selection Mixed Integer Linear Program (MILP) to select from different realizations of cells such that power consumption is minimized without violating delay constraints Sum of dynamic and leakage power is minimized A set of variables for each cell to support different Sizes Supply voltages Threshold voltages Achieved 79% power saving on an average Limitation: depends on diversity of the cell library Reference: Y. Zhang, X. Hu and D. Z. Chen, “Cell Selection from Technology Libraries for Minimizing Power”, DAC ‘01

18 May 18, 2004 MS Defense: Uppalapati 18 Talk Progress Motivation Background Prior Work Proposed Design Flow Results Conclusion and Future Work

19 May 18, 2004 MS Defense: Uppalapati 19 New Glitch Removing Solution Balanced the differential delays at cell inputs: Using delay elements called Resistive Feedthrough cells Automated the delay element Generation Insertion into the circuit

20 May 18, 2004 MS Defense: Uppalapati 20 Proposed Design Flow Modified linear program Resistive feed though cell generation: Fully automated Scalable to large ICs Layout generation of modified netlist Can use any place-and-route tool Design Entry Tech. Mapping Layout Remove Glitches

21 May 18, 2004 MS Defense: Uppalapati 21 First Attempt – Did not work: Modified Linear Program Changes from Raja’s linear program : Gate delays – constants Wire delays – only variables Constrained solution space Large number of buffers inserted Buffers consume power may exceed the power saved Circuit# gates# bufs 4-bit ALU9036 c432240120 C499618396 C880383217 C1355546414 C26701193162

22 May 18, 2004 MS Defense: Uppalapati 22 Comparison of Delay Elements Delay element Average delay (ns) Delay/ Power Delay/ Area I0.280.22.03 II0.594.430.05 III0.725.540.11 IV0.631.050.16 II. n diffusion capacitor III. Polysilicon resistor IV. Transmission gate I. Inverter pair Resistor shows Maximum delay Minimum power and area per unit delay Hence, best delay element Resistive feed through cell A fictitious buffer at logic level

23 May 18, 2004 MS Defense: Uppalapati 23 Resistive Feed-through Cell A parameterized cell Physical design is simple – easily automated No routing layers(M2 to M5) used – not an obstruction to the router R = R □ *(length of poly) Width of poly

24 May 18, 2004 MS Defense: Uppalapati 24 RC Delay Model Used to find the resistance value for a given delay Delay depends on load capacitance Number of fan-outs SPECTRE simulations done for varying R and C L values C L is varied in steps of transistor pairs Vin R CLCL

25 May 18, 2004 MS Defense: Uppalapati 25 RC Delay Model (cont’d…) C L varies during transition Model not perfectly linear Measured data stored as a 3D lookup table Average of signal rise and fall delays Linear interpolation between two points T PLH + T PHL 2 T P =

26 May 18, 2004 MS Defense: Uppalapati 26 Detailed Design Flow Design Entry Tech. Mapping Layout Remove Glitches Find delays from LP Find resistor values from lookup table Generate feed through cells and modify netlist

27 May 18, 2004 MS Defense: Uppalapati 27 Talk Progress Motivation Background Prior Work Proposed Design Flow Results Conclusion and Future Work

28 May 18, 2004 MS Defense: Uppalapati 28 Experimental Procedure Extract cell delays from initial layout SPECTRE simulation LP solver: CPLEX in AMPL C program to generate the input files Physical design of feed through cells and insertion of fictitious buffers PERL script Place-and-Route Silicon Ensemble from Cadence

29 May 18, 2004 MS Defense: Uppalapati 29 Power Estimation Logic level Event-driven delay simulator to count the transitions Power α # transitions × # fanouts Post layout SPECTRE simulator to measure current through the power rail Average power calculated by integration

30 May 18, 2004 MS Defense: Uppalapati 30 Results New Standard Cell Based Design Raja et. al. 4 bit ALU29.523.7N/A c432114.050.035.0 C49986.032.029.0 C88098.043.044.0 C135522.068.356.0 C267014.030.031.0 Power Saved(%) Area Overhead(%) Power Saved(%) Circuit

31 May 18, 2004 MS Defense: Uppalapati 31 Glitch Elimination on net86 in the 4bit ALU Source: Post layout simulation in SPECTRE

32 May 18, 2004 MS Defense: Uppalapati 32 Energy Saving in 4 bit ALU

33 May 18, 2004 MS Defense: Uppalapati 33 Layouts of c880 Original layout of c880 Optimized layout of c880

34 May 18, 2004 MS Defense: Uppalapati 34 Talk Progress Motivation Background Prior Work Proposed Design Flow Results Conclusion and Future Work

35 May 18, 2004 MS Defense: Uppalapati 35 Conclusions Successfully devised a glitch removal method for the standard cell based design style Does not require re-design of the mapped cells Does not increase the critical path delay Scalable with technology The modified design flow is well automated Maintains the low design time of this style On an average Dynamic power saving: 41% Area overhead: 60%

36 May 18, 2004 MS Defense: Uppalapati 36 Future Work Diverse target cell library Cells of different propagation delays LP model needs to be changed Might become an ILP 70% of necessary delays below 2 ns Interconnect delays can be used Placement and routing algorithms need to be controlled An NP complete problem

37 May 18, 2004 MS Defense: Uppalapati 37 Future Work (contd…) Reference: 1997 International Technology Roadmap for Semiconductors

38 May 18, 2004 MS Defense: Uppalapati 38 References V. D. Agrawal, “Low Power Design by Hazard Filtering”, VLSI Design 1997 T. Raja, V. D. Agrawal and M. L. Bushnell, “Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program”, VLSI Design 2003 Y. Zhang, X. Hu and D. Z. Chen, “Cell Selection from Technology Libraries for Minimizing Power”, DAC 2001 J. M. Masgonty, S. Cserveny, C. Arm and P. D. Pfister, “Low-Power Low-Voltage Standard Cell Libraries with a Limited Number of Cells”, PATMOS 2001

39 May 18, 2004 MS Defense: Uppalapati 39 THANK YOU

40 May 18, 2004 MS Defense: Uppalapati 40 Prior Work : Existing Low Power Design Techniques System Architectural RT - Level Logic Physical HW/SW co-design, Custom ISA, Algorithm design Scheduling, Pipelining, Binding Clock gating, State assignment, Retiming Logic restructuring, Technology mapping Fan-out Optimization, Buffering, Transistor sizing, Glitch elimination

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