1. PACS IBDR 27/28 Feb 2002 Herschel PACS SPU - IAC1 Herschel PACS - IBDR SIGNAL PROCESSING UNIT - SPU - HW Unit, Start-up SW and Low-level SW Drivers José M. Herreros INSTITUTO DE ASTROFÍSICA DE CANARIAS - IAC -

2. PACS IBDR 27/28 Feb 2002 Herschel PACS SPU - IAC2 CONTENTS 1.Electrical Design Evolution 2.Budgets. 3.Box Outlines and Block Diagrams. 4.Software 5.Model Philosophy. 6.CRISA Status Report. 7.Critical / Problem Areas. 8.Schedule.

3. PACS IBDR 27/28 Feb 2002 Herschel PACS SPU - IAC3 ELECTRICAL DESIGN EVOLUTION CPU BOARD: –Program and Data Memory sizes increase due to: PACS data reduction/compression requirements UTMC memories instead of WhiteElectronics –PSC ASIC Design consolidation (TEMIC manufacturer) DC/DC CONVERTER: –Removal of external synchronization

4. PACS IBDR 27/28 Feb 2002 Herschel PACS SPU - IAC4 New MEMORY ORGANIZATION

5. PACS IBDR 27/28 Feb 2002 Herschel PACS SPU - IAC5 SPU UNIT BUDGETS

6. PACS IBDR 27/28 Feb 2002 Herschel PACS SPU - IAC6 PACS SPU BOX OUTLINE LFI-REBA PACS-SPU

7. PACS IBDR 27/28 Feb 2002 Herschel PACS SPU - IAC7 SPU FUNCTIONAL BLOCK DIAGRAM The CPU board is designed to include as maximum:  One DSP working at 18 MHz  One 32 KW x 48 Boot PROM bank  Three EDAC protected SRAM memory banks:  512 KW x 48 for Program RAM  512 KW x 32 for Data RAM  512 KW x 32 for expansion of Data RAM  One EDAC protected up to 256 KW x 48 EEPROM memory bank.  Three IEEE1355 DS links including one common 8KWx32 Dual Port RAM buffer  Two PSC ASICs including:  Watchdog, OBT and 32 bit GP Timers.  EDAC logic and Interrupt management.  Programmable Address decoding and Wait State generator.  One Auxiliary Board Interface, including:  One redundant interface to the MIL-STD- 1553 bus including one 8KWx16 Dual Port RAM buffer.  One Mother Board Interface Each CPU board executes its own specific Start Up and Application Software.

8. PACS IBDR 27/28 Feb 2002 Herschel PACS SPU - IAC8 CPU BLOCK DIAGRAM

9. PACS IBDR 27/28 Feb 2002 Herschel PACS SPU - IAC9 DC/DC CHARACTERISTICS Input Voltage Operation from 26 to 32 Volts Use of a SMART Converter (Buck / Push-Pull with conductance Control) Buck Switching Frequency Operating around 130kHz Outputs Voltages as follow : –+5 Volts –+/- 15 Volts

10. PACS IBDR 27/28 Feb 2002 Herschel PACS SPU - IAC10 DC/DC BLOCK DIAGRAM

11. PACS IBDR 27/28 Feb 2002 Herschel PACS SPU - IAC11 DAU BLOCK DIAGRAM

12. PACS IBDR 27/28 Feb 2002 Herschel PACS SPU - IAC12 ASIC BLOCK DIAGRAM

13. PACS IBDR 27/28 Feb 2002 Herschel PACS SPU - IAC13 START-UP SW AND LOW-LEVEL SW DRIVERS Both SWL-SPU and LWL-SPU contain their own separate but identical PROM SW activated simultaneously during the switch-on of the SPU or under a SW reset. The Start-Up SW will perform the necessary functions to boot the unit at power up, perform a health self-test and start the Application SW giving it the control. The Low-Level SW drivers is a set of primitives (source/object code) to be compiled/linked with the different application software package. CONTEXT DIAGRAM

14. PACS IBDR 27/28 Feb 2002 Herschel PACS SPU - IAC14 PACS SPU START-UP SW ARCHITECTURE

15. PACS IBDR 27/28 Feb 2002 Herschel PACS SPU - IAC15 SPU MODEL PHILOSOPHY

16. PACS IBDR 27/28 Feb 2002 Herschel PACS SPU - IAC16

17. PACS IBDR 27/28 Feb 2002 Herschel PACS SPU - IAC17 CRISA STATUS REPORT (1/4) 1.Contract / Commercial / Management Phase 1 - conditioned final milestone - achieved on W51 Phase 2 - 2nd progress Milestone - took place on W51. Phase 3 ITT not set. 2.HW & System Engineering System engineering activity: Production of revised system documents for the system BDR (HW/SW ICD). Design engineering activity: DC/DC Electrical design consolidated. PCB design finished. 3.SW Engineering Integration under way. Little adaptations being implemented in parallel with the tests.

18. PACS IBDR 27/28 Feb 2002 Herschel PACS SPU - IAC18 CRISA STATUS REPORT (2/4) 4.ASIC Development ASIC tests and integration fully completed in representative FPGA. Now working in the ‘coberture’ (failure simulations) as part of the industrial file for procurement. This activity resulting more complex than expected will be finished beginning W10. The complete dossier is expected to be ready by end March 2002. 5.Physical & Verification Engineering None. 6.Unit Tester Engineering Unit tester HW & SW (1st) in work area. Complementary ‘test set’ ready in work area.

19. PACS IBDR 27/28 Feb 2002 Herschel PACS SPU - IAC19 CRISA STATUS REPORT (3/4) 7.Procurement & Parts Engineering DC/DC CV PCB for AvMs ordered week #8. Last steps of the Procurement for AvM going on compatible with schedule. No critical conflict still envisaged. Changes to DCL (coming from DC/DC design) to be reported on February 22 nd 2002 to TLG and IAC. 8.MAI Activities New CPUs set under MAI, about 60% achieved. No conflict envisaged up to now in plant to fulfil delivery dates. Two boards already waiting to be tested. 1 st DAU and AUX ready for tests.

20. PACS IBDR 27/28 Feb 2002 Herschel PACS SPU - IAC20 CRISA STATUS REPORT (4/4) 9.Tests activities 1 st CPU under HW Characterisation. Timing problems detected outside the CPU, concretely within the NAIS test board (an auxiliary I/F board with the logic analyser used in test). Once confirmed this fact, tests have been normally resumed. They are satisfactorily running at good rhythm by now. SW (version 1) integration under way. Last steps performed consisting on the successful initiation of the 1355 / SCMS tests. 10.EMs / AvMs Delivery Schedule - no margin included - EM SPU ready for delivery: 15/03/02 EM REBA ready for delivery: 04/04/02 AvM SPU ready for delivery: 16/04/02 AvM SPU ready for delivery: 04/04/02

21. PACS IBDR 27/28 Feb 2002 Herschel PACS SPU - IAC21 CRITICAL / PROBLEM AREAS Financing for PACS-SPU and LFI-REBA Qualification stage: Confirmed un-officially. Funds expected for end of December not received. Negotiations in progress. ITT for Phase III: Qualification and QM Not started pending of receiving funds. Request for financing Phase IV: Flight Models To be made before 15 of March.