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Laboratoire de l’Accélérateur Linéaire (IN2P3-CNRS) Orsay, France 24 February 2003 News about SPECS system  SPECS system  SPECS-SLAVE chip  SPECS-SLAVE.

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Presentation on theme: "Laboratoire de l’Accélérateur Linéaire (IN2P3-CNRS) Orsay, France 24 February 2003 News about SPECS system  SPECS system  SPECS-SLAVE chip  SPECS-SLAVE."— Presentation transcript:

1 Laboratoire de l’Accélérateur Linéaire (IN2P3-CNRS) Orsay, France 24 February 2003 News about SPECS system  SPECS system  SPECS-SLAVE chip  SPECS-SLAVE mezzanine board  Ground isolation  Development schedule

2 LHCb week February 2003 D.Charlet PCI SPECS Master Board PCI connector PC mother board PCI SPECS Master board LVDS drivers 4 SPECS Masters + 1 SPECS Slave APEX 20K200E PQFP 240 PCI target interface PLX 9030 PQFP 176 RJ45 SPECS or JTAG LVDS bus SPECS or I2C LVDS bus SPECS LVDS bus PCI bus PLX local bus SPECS bus RJ45 LVDS drivers LVDS drivers LVDS drivers SPECS LVDS bus Firmware version 2.0

3 LHCb week February 2003 D.Charlet SPECS new implementation RJ 45 Differential to TTL MS_SDA MS_SCL SM_SDA SM_SCL RJ 45 Differential to TTL MS_SDA MS_SCL SM_SDA SM_SCL SPECS bus (4 diff pairs) (up to 100m) SPECS slave Mezzanine board SPECS master PCI board

4 LHCb week February 2003 D.Charlet On detector I2C implementation SDA SCL On detector Remote board OC SPECS slave Mezzanine board Detector board On detector chips vcc DS92LV010A

5 LHCb week February 2003 D.Charlet SPECS-SLAVE chip

6 LHCb week February 2003 D.Charlet Architecture of SPECS slave FPGA

7 LHCb week February 2003 D.Charlet SPECS slave chip pinout 1

8 LHCb week February 2003 D.Charlet SPECS slave chip pinout 2

9 LHCb week February 2003 D.Charlet SPECS slave mezzanine board

10 LHCb week February 2003 D.Charlet Functionalities of the mezzanine  8 switches will be available to fix the SPECS slave address and 4 for the broadcast group address (one by type of board for instance).  One PROM will allow the ECS system to get information about the concerned front-end element. It will be mounted on a socket.  8 software programmable I2C/JTAG differential outputs. Each of them can individually be dedicated to one type of bus.  One local I2C bus and one local JTAG bus.  One parallel bus.  One decoder for the channel B of the TTCrx will be implemented within the SPECS slave chip. It will decode the necessary functions (currently L0 counter reset and Test pulse). Others ?  One 32-bit static register to control the local environment (would 16 be enough ? ). We are looking at the possibility to put an 8 bit ADC on this board, for slow measurements like temperature, etc... The problem is actually to find a sufficiently rad-hard one …

11 LHCb week February 2003 D.Charlet SPECS slave mezzanine board implentation

12 LHCb week February 2003 D.Charlet Ground isolation implementation proposal Baracks 100m Top of detector Crate "Controller" Specs slave 21 boards Point to point Clock distribution Optional insulation crate Optical link ?

13 LHCb week February 2003 D.Charlet Schedule for the SPECS system Firmware version 2.0 Beta PCI Master board vesrsion 1 Firmware version 2.0 Windows Software FebruaryMarchApril Version 2.1 Documentation Linux Software May PCI Master board version 2 JuneJuly SPECS-Slave mezzanine board


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