1. Computer Architecture - Quiz 3, answers Answer 1  IF: Read instruction from memory (1.2ns or 2*0.7ns), compute PC+4 (0.6ns). The super-pipeline has 2 IF stages of 0.7ns.  ID: Registers can be read from the RF in 0.7ns. The branch target is computed in 0.6ns (PC + 16-bit offset), both can be done in parallel. However comparing both operands (by XOR) is done in 0.5ns after the register are read. This stage must be split as well. Thus we have 1 stage of 0.7ns and 1 stage of 0.5n.  EX: Adding two 32-bit numbers can be broken down into adding a 32-bits with the lower 16-bits, and adding the 32-bit result and carry with the higher 16-bits. 2 stages of 0.6ns.  MEM: 2 stages of 0.6ns.  WB: Write to the RF in 0.7ns.  Total: 9 stages (IF1,IF2,ID1,ID2,EX1,EX2,MEM1,MEM2,WB) of 0.7ns each.

2. Computer Architecture - Quiz 3, answers Answer 2 ld$1,0($gp)ld$2,4($gp)ld$3,8($gp) addi$6,$6,1subi$7,$7,1addi$gp,$gp,12 add$4,$1,$2slt$8,$6,$7add$9,$9,$3 bne$8,$zero,loopadd$9,$9,$4  The CPI is 4/11 = 0.36

3. Computer Architecture - Quiz 3, answers Answer 3 Unrolled Version addi$t7,$zero,100 addi$t8,$zero,1 Do:ld$t1,0($s0) ld$t10,4($s1)addi$t0,$t0,2 add$t5,$t1,$t1 addi$s0,$s0,8 add$t15,$t10,$t10 slt$t2,$t0,$t7 sw$t5,0($s1)addi$s0,$s0,8 sw$t15,-4($s1)beq$t2,$t8,Do The IPC of the loop is 11/6 = 1.83

4. Computer Architecture - Quiz 3, answers Answer 4 lw$t0,0($gp) add$t1,$t2,$t3 sub$t3,$t1,$t0  There is no imprecise exception in this case.  The lw might cause a segmentation fault, but sub won’t be executed before it because of a dependency on $t0.  add might be executed out-of-order but the value in $t1 will be the same thing every time. It will be $t2+$t3.