1. Hasim Joel Emer †‡ Michael Adler †, Artur Klauser †, Angshuman Parashar †, Michael Pellauer ‡, Murali Vijayaraghavan ‡ † VSSAD Intel ‡ CSAIL MIT

2. 2007.05.14Hasim2 Overview Goal –Produce compelling evidence for architecture ideas Requirements –Cycle accurate simulation –Representative simulation length –Software development (often) Current approach –Mostly software simulation (10 KHz to 1 KHz) New approach –Build a performance model in an FPGA

3. 2007.05.14Hasim3 FPGA-based approaches Prototyping –Build a logically isomorphic representation of the design Modeling –Build a performance simulation in gates Hybrids –Build something that is partially a prototype and partially a model

4. 2007.05.14Hasim4 Recreate Asim in hardware Modularity Inter-module communication Functional/Timing Partitioning Modeling Utilities

5. 2007.05.14Hasim5 Why modularity? Speed of model development Shared components between products Reuse across generations Encourages isomorphism to design Improved fidelity Facilitates speed/fidelity trade-offs Architectural experimentation Factorial development and evaluations Sharing

6. 2007.05.14Hasim6 ASIM Module Hierarchy S MCNDRXCWFB

7. 2007.05.14Hasim7 ASIM Module Selection B B B B S MCN DRXCWF B B

8. 2007.05.14Hasim8 DRXCWF DRXCWF S MCN CMN Module Selection S B B B B B B

9. 2007.05.14Hasim9 Module Replacement B B B B S MCN DRXCWF B X

10. 2007.05.14Hasim10 (H)ASIM Module Hierarchy

11. 2007.05.14Hasim11 Communication C DRXCWF NN

12. 2007.05.14Hasim12 Named connections SD A-outA-in

13. 2007.05.14Hasim13 Model and FPGA Cycles Module A Module B Port A1.11.21.32.12.2 B1.12.12.22.3 12345678 A1.11.21.32.12.2 B1.12.12.22.3 12345678 Port

14. 2007.05.14Hasim14 Functional/Timing Decomposition ISA semantics Platform semantics Micro-architecture Timing Partition Functional Partition Fetch(PC) … Instruction Simplifies timing model Amortize functional model design effort over many models Can be pipelined for performance Can be FPGA-friendly design Can be split across hardware and software

15. 2007.05.14Hasim15 Execute@execute phases Fetch instruction Speculatively execute instruction Read memory * Speculatively write memory * (locally visible) Commit or Abort instruction Write memory * (globally visible) * Optional depending on instruction type

16. 2007.05.14Hasim16 Execution in phases FDXRCFDXWCWFDXC Assertion: All data dependencies can be represented in these phases FDXRA FDXXCW

17. 2007.05.14Hasim17 HASim: Partitioning Overview Token Gen Dec ExeMemLCom GComFet Timing Partition Memory State Register State RegFile Functional Partition

18. 2007.05.14Hasim18 Common Infrastructure Modules Inter-module communication Statistics gathering Event logging Debug Tracing Simulation control …

19. 2007.05.14Hasim19 Bluespec (Asim-style) module module [HAsim_module] mkCache#() (Empty); Port#(Addr) req_port <- mkSendPort(‘a2cache’); Port#(Bool) resp_port <- mkRecvPort(‘cache2a’); TagArray tagarray <- mkTagArray(); rule cycle(True); Maybe#(Addr) mx = req_port.get(); if (isValid(mx)) resp_port.put(tagarray.lookup(validValue(mx))); endrule endmodule

20. 2007.05.14Hasim20 Bluespec (Asim-style) submodule module mkTagArray(TagArray); RegFile#(Bit#(12),Bit#(4)) tagArray<- mkRegFileFull(...); method Bool lookup(Bit#(16) a); return (tagArray.sub(getIndex(a)) == getTag(a)); endmethod function Bit#(4) getTag(Address x); return x[15:12]; endfunction function Bit#(12) getIndex(Address x); return x[11:0]; endfunction endmodule

21. 2007.05.14Hasim21 Support functions - stats Module Stat Counter Module Stat Counter Module Stat Counter Stat Dumper module mkCache#(...) (Empty);... cache_hits <- mkStat(...);... hit=tagarray.lookup(...); if (hit) cache_hits.increment(); endif... endmodule

22. 2007.05.14Hasim22 2Dreams

23. 2007.05.14Hasim23 Support functions - events Module Event Reg Module Event Reg Module Event Reg Event Dumper module mkCache#(...) (Empty);... cache_event <- mkEvent(...);... hit=tagarray.lookup(...); cache_event.report(hit);... endmodule

24. 2007.05.14Hasim24 Support functions – global controller Module Controller Module Controller Module Controller Global Controller module mkCache#(...) (Empty);... ctrl <- mkCntrlr(...);... rule (ctrl.run())... endrule endmodule

26. 2007.05.14Hasim26 FPGA-based prototype Prototyping Catch-22…

27. 2007.05.14Hasim27 Module Instantiation U DRXCWF MCN C DRXCWF M C DRXCWF

28. 2007.05.14Hasim28 Factorial Coding/Experiments SC S MCN SM RC S MCN SM SC S MCN RM RC S MCN RM

29. 2007.05.14Hasim29 HAsim: Current status - models Simple RISC functional model operating – Simple RISC ISA – Pipelined multi-phase instruction execution – Supports speculative OOO design Physical Reg File and ROB Small physically addressed memory Fast speculative rewinds Instruction-per-cycle (APE) model –Runs simple benchmarks on FPGA Five stage pipeline –Supports branch mis-speculation –Runs simple benchmarks (in software simulation) X86 functional model architecture under development

30. 2007.05.14Hasim30 Connections Implement Ports foo bar foo baz PM (Module Tree w. Connections) PM (Hardware Modules w. Wrappers) bar foo baz Implemented via connections.

31. 2007.05.14Hasim31 Timing Model Resources (Fast) OOO, branch prediction, three functional units, 32KB 2-way set associative ICache and DCache, iTLB, dTLB 2142 slices (15% of a 2VP30) 21 block RAMs (15% of a 2VP30) Configurable cache model 32KB 4-way set associative cache with 16B cache-lines –165 slices (1% of a 2VP30) –17 block RAMs (12% of a 2VP30) 2MB 4-way set-associative cache with 64B cache-lines –140 slices (1% of a 2VP30) –40 block RAMs (29% of a 2VP30) Current FPGAs (4VFX140) 142,128 slices 552 block RAMs 2 PowerPCs