1. EECE579: Digital Design Flows
Usman Ahmed
Dept. of ECE
University of British Columbia

2. Implementing Digital Circuits
Digital Circuit Implementation Approaches
Custom
Semicustom
Cell-based
Array-based
Standard Cells
Gate Arrays
Structured ASICs
Macro Cells
FPGA's
Compiled Cells

3. Implementing Logic Circuits
Design Iteration
Implementing Logic Circuits
HDL
Logic Synthesis
Floorplanning
Placement
Routing
Tape-out
Circuit Extraction
Pre-Layout Simulation
Post-Layout Simulation
Structural
Physical
Behavioral
Design Capture

4. Standard Cell Design Library of cells that implement different gates
Cells can have different width but all cells have same height
(hence Standard Cells)
Many variants of the same cell

5. Standard Cell Design Logic Synthesis
Transform the HDL description into library cells
Placement
Where to place a cell ?
Routing
Connect the placed cells.

6. Standard Cell Design Optimizations: Gate Resizing Buffer Insertion
In-place Re-synthesis

7. Standard Cell Design: An Example

8. Standard Cell Design
Routing channel can be narrowed if more interconnect layers are available

9. Standard Cell Design: New Generation
Cell-structure hidden under interconnect layers

10. Standard Cell Design: Summary
Used only for the high-speed or low-power applications
Very expensive, and time consuming
(> $2M just for the mask costs)
Very high re-spin cost

11. FPGAs
FPGA: Field-Programmable Gate Array

12. What’s Inside an FPGA? Logic Blocks - used to implement logic
- lookup tables and
flip-flops
Altera: LABs
Xilinx: CLBs

13. What’s Inside an FPGA? I/O Blocks - interface off-chip
- can usually support
many I/O Standards

14. What’s Inside an FPGA?

15. Logic Block: Basic Logic Gate: Lookup-Table Inputs Bit-Stream
Function of each lookup table can be configured by shifting in bit-stream.
Inputs
Bit-Stream

16. Logic Clusters Several lookup tables are grouped into “clusters”
- Typically 8 to 10 lookup
tables per cluster
Connections between lookup tables in the same cluster are fast
Connections between lookup tables in different clusters are slow

17. What’s Inside an FPGA?

18. Reconfigurable Logic:
Connect Logic Blocks using Fixed Metal Tracks and Programmable Switches

19. Reconfigurable Logic:
Connect Logic Blocks using Fixed Metal Tracks and Programmable Switches

20. Implementing Systems in an FPGA
FPGA Fabric
Embedded memories
Embedded PowerPC
Hardwired multipliers
Xilinx Vertex-II Pro
High-speed I/O

21. Disadvantages of FPGAs:
"Instant Manufacturability": reduces time to market
Cheaper for small volumes because you don’t need to pay for fabrication
means you don’t need to be a big company to make a chip
Relaxes Designers -> relaxed designers live longer!
Disadvantages of FPGAs:
Slower than custom or standard cell based chips
Cannot get as much circuitry on a single chip
Today: ~ 1M gates is the best you can do
~ 200 MHz is about as fast as you can get
For large volumes, it can be more expensive than gate arrays and custom chips

22. Structured ASICs
Combines good features of FPGAs and Standard Cell ASICs

23. Logic Blocks Choices Configurability Fine Grained Medium Grained
Basic gates: NAND, NOR, XOR, FF etc.
Medium Grained
Lookup Tables
Coarse Grained
Multi-input, Multi-output blocks (e.g., PLAs)
Configurability
SRAM cells
Vias
Lower Level (e.g., between M1 and M2)
Upper Level (Via stacks brought up to the configurable layers)

24. Routing Fabrics Metal and Via Programmable Via Programmable
More flexibility, more efficiency
Employed in most structured ASIC offerings
Via Programmable
Regular, easy to manufacture
Metal is fixed and every segment may not be fully utilizable,
→ Can be Inefficient

25. Design Flows

26. Design Flows

27. Design Flows

28. Design Flows

29. Design Flows

30. Implementing Logic Circuits
Design Iteration
Implementing Logic Circuits
HDL
Logic Synthesis
Floorplanning
Placement
Routing
Tape-out
Circuit Extraction
Pre-Layout Simulation
Post-Layout Simulation
Structural
Physical
Behavioral
Design Capture