1. Defect Tolerance for Yield Enhancement of FPGA Interconnect Using Fine-grain and Coarse-grain Redundancy Anthony J. Yu August 15, 2005

2. 2 Outline Introduction and motivation Introduction and motivation Previous works Previous works New architectures New architectures Coarse-grain redundancy (CGR) Coarse-grain redundancy (CGR) Fine-grain redundancy (FGR) Fine-grain redundancy (FGR) Comparisons Comparisons Conclusions Conclusions

3. 3 Introduction and Motivation Scaling introduces new types of defects Scaling introduces new types of defects Number of defects expected to increase as chip density increases Number of defects expected to increase as chip density increases As a result, chip yield is on the decline As a result, chip yield is on the decline FPGAs are mostly interconnect FPGAs are mostly interconnect To improve yield (and revenue), we must tolerate multiple interconnect defects To improve yield (and revenue), we must tolerate multiple interconnect defects

4. 4 General Defect Tolerant Techniques Defect-tolerant techniques minimize impact (cost) of manufacturing defects Defect-tolerant techniques minimize impact (cost) of manufacturing defects FPGA defect-tolerance can be loosely categorized into three classes: FPGA defect-tolerance can be loosely categorized into three classes: Software Redundancy – use CAD tools to map around the defects Software Redundancy – use CAD tools to map around the defects Hardware Redundancy – incorporate spare resources to assist in defect correction (eg. Spare row/column) Hardware Redundancy – incorporate spare resources to assist in defect correction (eg. Spare row/column) Run-time Redundancy – protection against transient faults such as SEUs (eg. TMR) Run-time Redundancy – protection against transient faults such as SEUs (eg. TMR)

5. 5 Previous work – 1 – Xilinx Xilinx’s Defect-Tolerant Approach Xilinx’s Defect-Tolerant Approach Customer (knowingly) purchases “less that perfect” parts Customer (knowingly) purchases “less that perfect” parts Customer gives Xilinx configuration bitstream Customer gives Xilinx configuration bitstream Xilinx tests FPGA devices against bitstream Xilinx tests FPGA devices against bitstream Sells FPGA parts that “appear” perfect Sells FPGA parts that “appear” perfect Defects avoid the bitstream Defects avoid the bitstream Limitation: Limitation: Chips work only with given bitstream – no changes! Chips work only with given bitstream – no changes!

6. 6 Previous work – 2 – Altera Altera’s Defect-Tolerant Approach Altera’s Defect-Tolerant Approach Customer purchases “seemingly perfect” parts Customer purchases “seemingly perfect” parts Make defective resources inaccessible to user Make defective resources inaccessible to user Coarse-grain architecture Coarse-grain architecture Spare row and column in array (like memories) Spare row and column in array (like memories) Defective row/column must be bypassed Defective row/column must be bypassed Use the spare row/column instead Use the spare row/column instead Limitation: Limitation: Does not scale well (multiple defects) Does not scale well (multiple defects)

7. 7 Objectives Problem Problem FPGA yield is on decline because of aggressive technology scaling FPGA yield is on decline because of aggressive technology scaling Important objectives to improve yield: Important objectives to improve yield: Tolerate interconnect defects (dominates area) Tolerate interconnect defects (dominates area) Tolerate multiple defects (future trend) Tolerate multiple defects (future trend) Preserve timing (no timing re-verification) Preserve timing (no timing re-verification) Fast correction time (production use) Fast correction time (production use)

8. 8 Contributions New fine-grain redundancy architecture New fine-grain redundancy architecture Coarse-grain architecture with multiple spare rows and columns Coarse-grain architecture with multiple spare rows and columns Detailed evaluation of fine-grain and coarse-grain redundancy Detailed evaluation of fine-grain and coarse-grain redundancy Area, delay, yield estimates Area, delay, yield estimates Publications: Publications: Non-redundant architecture paper, at FPT’04 Non-redundant architecture paper, at FPT’04 Fine-grain architecture paper, to appear in FPL’05 Fine-grain architecture paper, to appear in FPL’05 Yield comparison paper, to appear in FPT’05 Yield comparison paper, to appear in FPT’05

9. 9 Non-redundant Interconnect Switch OLD(bidirectional)MODERN(directional) HIGH-LEVEL MODEL

10. 10 Coarse-grain Redundancy (CGR)

11. 11 So…what’s wrong with it?

12. 12 Improving yield for CGR – Adding Multiple Global Spares Add multiple global spare to traditional CGR Add multiple global spare to traditional CGR Global spares can be used to repair any defective row/column in the array Global spares can be used to repair any defective row/column in the array Wire extensions are now longer Wire extensions are now longer

13. 13 Yield Impact of Multiple Global Spares

14. 14 Increasing Area+Delay Overhead 1 GLOBAL SPARE 2 GLOBAL SPARES 4 GLOBAL SPARES MAY BE IMPRACTICAL !!! NO SPARES MORE SPARES  MORE MUX OVERHEAD IN EVERY SWITCH ELEMENT

15. 15 Fine-grain Redundancy (FGR) – Avoidance by Shifting

16. 16 Implementation Overview

17. 17 FGR Switch Element Details Upstream Switch Block Downstream Switch Block Defect

18. 18 FGR Implementation Comparison

19. 19 FGR Architectural Summary Several implementations of FGR evaluated: Several implementations of FGR evaluated: Implementation with best yield improvement (EM22) Implementation with best yield improvement (EM22) Area +50%, delay + 20% Area +50%, delay + 20% Implementation with lowest yield improvement (EN11) Implementation with lowest yield improvement (EN11) Area +35%, delay +25% Area +35%, delay +25% Perfect chips can be sold as interconnect-enhanced FPGAs Perfect chips can be sold as interconnect-enhanced FPGAs Allow router to use spare routing resources (muxes, tracks) Allow router to use spare routing resources (muxes, tracks) Gives more routing flexibility Gives more routing flexibility True area and delay overhead are 10-20% and 5-25% True area and delay overhead are 10-20% and 5-25%

20. 20 Comparison between FGR and CGR – FGR Tolerates Tens of Defects

21. 21 Estimated Area overhead at equal yield (80%) * CGR-G1 can only tolerate 1-2 defects

22. 22 Limitations of Study & Architectures FGR FGR Does not tolerate defects in the logic Does not tolerate defects in the logic Cannot tolerate clustered defects Cannot tolerate clustered defects Requires a detailed fault map Requires a detailed fault map CGR CGR Assumes that all defects can be corrected with a single row/column Assumes that all defects can be corrected with a single row/column Bypass circuitry is approximated Bypass circuitry is approximated

23. 23 Conclusions CGR is effective for 1 or 2 defects CGR is effective for 1 or 2 defects FGR meets desired objectives: FGR meets desired objectives: Tolerates multiple randomly distributed defects Tolerates multiple randomly distributed defects Defect correction does not perturb timing Defect correction does not perturb timing Tolerates an increasing number of defects as array size increases Tolerates an increasing number of defects as array size increases Correction can be applied quickly Correction can be applied quickly FGR potentially capable of correcting crosstalk faults, but is not explored in thesis FGR potentially capable of correcting crosstalk faults, but is not explored in thesis

24. 24 Contributions New fine-grain redundancy architecture New fine-grain redundancy architecture Coarse-grain architecture with multiple spare rows and columns Coarse-grain architecture with multiple spare rows and columns Detailed evaluation of fine-grain and coarse-grain redundancy Detailed evaluation of fine-grain and coarse-grain redundancy Detailed circuit-level design  improved area, delay estimates Detailed circuit-level design  improved area, delay estimates Yield comparison Yield comparison Publications: Publications: Non-redundant architecture paper, at FPT’04 Non-redundant architecture paper, at FPT’04 Fine-grain architecture paper, to appear in FPL’05 Fine-grain architecture paper, to appear in FPL’05 Yield comparison paper, to appear in FPT’05 Yield comparison paper, to appear in FPT’05

25. Thank you! anthonyy@ece.ubc.ca

26. 26 Improving yield for CGR – Adding Multiple Local Spares Divide FPGA into subdivisions Divide FPGA into subdivisions Each subdivision has local spare(s) Each subdivision has local spare(s) Distributes spares across chip Distributes spares across chip Reduces mux area overhead (of Global scheme) Reduces mux area overhead (of Global scheme) Limitation: Limitation: Spare(s) can only repair defect within the subdivision Spare(s) can only repair defect within the subdivision

27. 27 Yield Impact of Multiple Local Spares (not as good as Global with same # spares)

28. 28 Summary As the density of FPGAs increase, they become increasingly susceptible to manufacturing defects As the density of FPGAs increase, they become increasingly susceptible to manufacturing defects Defect-tolerant techniques alleviate this growing problem Defect-tolerant techniques alleviate this growing problem Depending on the desired level of protection, we can apply different techniques Depending on the desired level of protection, we can apply different techniques At low defect rates, the coarse-grain spare row and column approach has lower overhead than the fine-grain approach At low defect rates, the coarse-grain spare row and column approach has lower overhead than the fine-grain approach At the same area overhead, the fine-grain approach can tolerate more defects than the spare row and column approach At the same area overhead, the fine-grain approach can tolerate more defects than the spare row and column approach