1. PSI - Jun. 27th, 20061 Status of the electronics systems of the MEG experiment

2. PSI - Jun. 27th, 20062 Electronic chain 216 630 Active Splitter 1:1 4:1 Active Splitter 1:1 4:1 Active Splitter 1:1 4:1 Ramp 60120 Pre-Amp 8:1 PMT LXe HV PMT lateral front TC HV APD PMT bars fibers DC HV Wires Strips Pre-Amp 576 1156 atten DRS 5 crates 512 Hit registers 4 boards Trigger 32 3 crates Aux. devices

3. PSI - Jun. 27th, 20063 DAQ and control 6 crates DRS Hit registers Trigger 3 crates 20 MHz clock start stop sync Trigger signal Event number Trigger type Trigger Busy Error Ancillary system  E5 area ‘counting room’ PC (Linux) Front-End PCs Run start Run stop Trigger config Main DAQ PC PC (Linux) Gigabit Ethernet On-line farm PC (Linux) storage PC (Linux) Event builder

4. PSI - Jun. 27th, 20064 HV

5. PSI - Jun. 27th, 20065 HV Active down regulation of an external HV supply PSI design 10 chn per board 180 chn per 3 HE crate Back side connector Total of 6 crates Active down regulation of an external HV supply PSI design 10 chn per board 180 chn per 3 HE crate Back side connector Total of 6 crates 4 different requirements: –Lxe: 1000V, 100 uA –TC bars: 2400V, 1 mA –TC curved: 500V, <1 uA –DC: 2400V, ~1 uA Commercial HV supplies delivered Mass production in progress Installation in September

6. PSI - Jun. 27th, 20066 Splitters

7. PSI - Jun. 27th, 20067 Splitter layout ERNI high bandwidth output connector crosstalk with ERNI connector plus 2m cable is ~ 0.6% DRS Trigger Trigger or DRS Input Power

8. PSI - Jun. 27th, 20068 Backplane layout Test circuit was implemented on backplane Debug completed PCB production in progress, mounting in house

9. PSI - Jun. 27th, 20069 Crates Mechanic parts and fans delivered Power supplies delivered and tested Frontal panel Back panel Output (5V-36A)

10. PSI - Jun. 27th, 200610 Cables Inputs Single coaxial cable (RG178 – 9m long) bundled into a polyester braided sleeve Negligible crosstalk between cables. DRS outputs High bandwidth output (DRS) high density twisted pairs cable (0.68 pitch) 2 m long with one flat zone in the middle (Amphenol SPECTRASTRIP 68p) Trigger outputs –Low density twisted pairs cable (1.27 pitch) 2 m long with 2 flat zone (3M 34p/10p)

11. PSI - Jun. 27th, 200611 Splitter Summary Splitter –first prototype finished in may successfully –PCB production started the first of June –PCB production time one month –Component procurement in progress –Board mounting 2 weeks end of July –Board test 1 week –Boards ready by the beginning of September Backplane –Crates and power supply delivered –backplane production in Lecce Cables –Trigger cables ready –LXe cables in production –DRS cables in production Installation –Foreseen between September 5 and 20

12. PSI - Jun. 27th, 200612 TC

13. PSI - Jun. 27th, 200613 PMT ramp generator RAMP GEN. RAMP GEN. D/D S TC Analog Sign. Monitor NIM Signal for any possible use to Splitter B B B B Analog signals to DRS and trigger Passive Splitter PMT Dual Threshold OR Constant Fraction OR Leading edge discriminator to Splitters Signals to DRS 6U Eurocards boards 8 boards

14. PSI - Jun. 27th, 200614 Production PMT ramp generator Design of the final boards in progress Mass production September (?) system delivery 8 boards October (?) APD pre amplifiers First prototype with problems on IC and cross talk Second prototype design and test completed Mass production and test in progress system delivery end of July APD hit registers board design completed Production and test in progress system delivery (6 boards – 6U VME) end of July

15. PSI - Jun. 27th, 200615 Trigger

16. PSI - Jun. 27th, 200616 Trigger Boards Type1 Front end Type2 Ancill

17. PSI - Jun. 27th, 200617 System test 4 Type1 2 Type2 2 Ancillary Synchronous operation No transmission errors

18. PSI - Jun. 27th, 200618 Splitter-Type1 connection Alpha and cosmic muon events from the Pisa facility

19. PSI - Jun. 27th, 200619 Number of boards: summary table

20. PSI - Jun. 27th, 200620 Number of boards: status Boards Type1 48 funded 36 needed 40 delivered 8 not completely mounted 40 tested Boards Type2 10 funded 5 needed 10 delivered 10 tested Boards Ancill 8 funded 4 needed 4 delivered 4 not completely mounted 2 tested Front-End Boards 800 funded 576 needed 800 delivered 320 tested Done !

21. PSI - Jun. 27th, 200621 Type1 : VIRTEX II- PRO (XC2VP20-7-FF1152)  Type1-0 LXe front face  Type1-1 LXe lateral faces  Type1-2 LXe top,bottom and back face  Type1-3 TC bars  Type1-4 TC fibers  Type1-5 DC  Type1-6 Auxiliary devices  Type1-7 LXe back face x Type2 : VIRTEX II- PRO (XC2VP40-7-FF1152)  Type2-0 Final Level completed   Type2-1 LXe front+up/down faces  Type2-2 LXe lateral faces  Type2-3 TC  Firmware V1.0 Present Status

22. PSI - Jun. 27th, 200622 Board Type3

23. PSI - Jun. 27th, 200623 Board Type3 Type3 board 32 channels Number of boards for the LXe lateral sides(612 chn): 20 Boards design : ~ ready PCB prototype : end of July Component delivery: (12 weeks) ~ beginning of September Test: September Production: October Installation: end of October Modified Type1 boards to produce an auxiliary digitization of the LXe signals

24. PSI - Jun. 27th, 200624 Comments on trigger Installation -Ready: any time from beginning of Jul. to end of Aug. -Should follow the NaI moving system -Should precede the electronic integration Sep. -DAQ computers Configuration -Baseline version V1.0 written -Needs tuning, at least 1 month during purification -Needs analysis tools, under development Documentation -Hardware register list available -Almost available for Type1 -In progress for Type2

25. PSI - Jun. 27th, 200625 DRS

26. PSI - Jun. 27th, 200626 DRS DRS2 available for all channels New PMC card finished –Reduced noise 1.2 mV → 0.5 mV RMS –Self-calibration on card –Mass production started –cards expected in August PSI GPVME boards in production –Delivery end of August

27. PSI - Jun. 27th, 200627 DRS2 issues IssueSolution DRS2DRS3 Voltage nonlinearityCalibration with cubic splines in Front-end Clock nonlinearityTime calibration & frequency regulation Cross talk 1% @ 7ns risetime Redesign of CMC card with ERNI 68-pin connector and interleaved ground lines Temperature dependence - Calibration maybe possible to some extend - Keep electronics temperature constant - On-chip temperature compensation ? ( ) Self-heating of cells- Only use small signals (<0.5 V) - On-chip temperature compensation ( ) Ghost pulses- Veto trigger ~5us after cosmic or LED event - Veto trigger after other calorimeter hits? - Record 2us calorimeter history in each event? - Redesign sampling cell ? ? All issues could be resolved as planned

28. PSI - Jun. 27th, 200628 DRS3 DRS3 design finished Prototypes expected in August Tests foreseen at the end of the year

29. PSI - Jun. 27th, 200629 DRS3 layout Smaller “standard cells” Totally > 600,000 transistors Smaller package (QFP64) 12 channels/chip ROI readout and parallel readout to reduced dead time: 230  s → 50  s → 5  s Smaller “standard cells” Totally > 600,000 transistors Smaller package (QFP64) 12 channels/chip ROI readout and parallel readout to reduced dead time: 230  s → 50  s → 5  s

30. PSI - Jun. 27th, 200630 DRS and Trigger Crates Power distribution box Issue: “Splitter” rack cannot be accessed easily from back side! 20 cm

31. PSI - Jun. 27th, 200631 DAQ cluster

32. PSI - Jun. 27th, 200632 DAQ Cluster Layout 80 GB System Disk RAID 1 (Mirror) /home/meg 1.2 TG Data Disk RAID 5 80 GB System Disk RAID 1 (Mirror) 80 GB System Disk RAID 1 (Mirror) Back-End Front-End #1 Front-End #2... NFS /home/meg |-- root <- ROOTSYS |-- midas <- MIDASSYS |-- mxml |-- rome <- ROMESYS `-- meg <- MEGSYS |-- meganalyzer |-- megbartender |-- megmc `-- online |-- drivers |-- eventbuilder |-- frontend |-- slowcontrol | |-- bts | |-- calorimeter | `-- scfe |-- trigger `-- VPC /home/meg |-- root <- ROOTSYS |-- midas <- MIDASSYS |-- mxml |-- rome <- ROMESYS `-- meg <- MEGSYS |-- meganalyzer |-- megbartender |-- megmc `-- online |-- drivers |-- eventbuilder |-- frontend |-- slowcontrol | |-- bts | |-- calorimeter | `-- scfe |-- trigger `-- VPC VME-Interface SC-FE Data rate 100 MB/s

33. PSI - Jun. 27th, 200633 Front-end computers Back-end 1.2 TB disk Front-end #1 GBit Switch Two DAQ computer installed with DAQ software Remaining computers delivered Installation end of July

34. PSI - Jun. 27th, 200634 Offline Cluster Sun Fire x4100 quad core 4 GB Fiber Channel Switch 15 x 500 GB SATA Ordered on June 14 th : 20 cores + 30 TB disk Easily extensible Redundancy through GFS/GPFS file systems GBit link to online cluster requested GBit Ethernet

35. PSI - Jun. 27th, 200635 Slow control

36. PSI - Jun. 27th, 200636 SCS-2000 Replaces SCS-1001 unit 64 I/O lines (analog, digital, opto-coupler, PT100, etc.) Outputs stable during CPU firmware upgrade ( → BTS control) “Soft” fuse LED pulser (40 lines, computer controllable) Replaces SCS-1001 unit 64 I/O lines (analog, digital, opto-coupler, PT100, etc.) Outputs stable during CPU firmware upgrade ( → BTS control) “Soft” fuse LED pulser (40 lines, computer controllable)

37. PSI - Jun. 27th, 200637 BTS slowcontrol Slowcontrol back-end to MSCB slow control units Integrated in MIDAS history system Monitoring and control though MIDAS web pages More pages added as SC equipment gets operational

38. PSI - Jun. 27th, 200638 MIDAS history

39. PSI - Jun. 27th, 200639 Conclusions All the key elements of the electronic system are available for integration in September Some parts will arrive with ~1 month delay

40. PSI - Jun. 27th, 200640 Rack space