1. Jet algorithm/FPGA and tests by Attila Hidvégi

2. Content Status of the jet algorithm Status of the jet-FPGA Different kind of tests FIO-scanning Summary and Outlook

3. Status of the jet algorithm Minor modifications of the algorithm: – A threshold is passed when the clustersum is greater than (>) the threshold. – Saturationflag in an RoI vector is set when the arithmetical value of a selected clustersum is greater then or equal (>=) to 1023. This is different for the moment from what Eric wrote in his specifications so it needs to be discussed. – The software simulation will have to be updated too. A new approach to synthesize the algorithm is being developed where the number of stages (the latency) is defined by a single generic value. This is possible due to the register balancing function in newer versions of the synthesis tools.

4. Status of the jet-FPGA LV_DCI towards the G-Link did not seemed to work. Could be a software or hardware issue. Normal LVTTL does work however. Since the ROD didn’t supported the final RoI- format an extra version with the old RoI-format was created. Support for different clocks for the jet algorithm and G-Link controller was added. Except for the G-Link signal levels, everything was working right from the beginning …

5. Different kind of tests Jet algorithm: – A few number of random testvectors (256 events at a time) have been successfully tested with standalone softwares. – To properly verify the performance of the jet algorithm, the full range of the addertrees and comparators have to be tested more effectively: Properly distributed random values at different adder levels. More different events needs to be tested. Data flow: – Several millions of jet events have successfully passed using the online software. – The phase issue of the input data from the input-FPGAs into the jet-FPGA turned out to be due the fact that the input-FPGAs sent the data with the MSB first instead of the LSB.

6. FIO-scanning Working windows for the clock deskew 2 relative to clock deskew 1 needs to be determined for JEM-1.0. How the final solution should be done needs some more discussion. The mapping of every single signal needs to be verified. This, however, should only be done once.

7. Summary and Outlook Things are progressing well. Next week the FIOs will be tested. Hopefully the jet algorithm will be fully tested on this FPGA before next meeting.